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rtl arbiter fixes

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This commit is contained in:
Blaise Tine 2024-08-10 00:37:56 -07:00
parent 229641441f
commit c8d0357ac6
3 changed files with 36 additions and 45 deletions
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25
hw/rtl/libs/VX_fair_arbiter.sv
View file

@ -38,26 +38,27 @@ module VX_fair_arbiter #(
end else begin
reg [NUM_REQS-1:0] requests_r;
reg [NUM_REQS-1:0] grant_hist;
wire [NUM_REQS-1:0] requests_sel = requests_r & requests;
wire [NUM_REQS-1:0] requests_qual = (| requests_sel) ? requests_sel : requests;
wire [NUM_REQS-1:0] requests_sel = requests & ~grant_hist;
wire rem_valid = (| requests_sel);
wire [NUM_REQS-1:0] requests_qual = rem_valid ? requests_sel : requests;
always @(posedge clk) begin
if (reset) begin
requests_r <= '0;
grant_hist <= '0;
end else if (grant_ready) begin
requests_r <= requests_qual & ~grant_onehot;
grant_hist <= rem_valid ? (grant_hist | grant_onehot) : grant_onehot;
end
end
VX_priority_arbiter #(
.NUM_REQS (NUM_REQS)
) priority_arbiter (
.requests (requests_qual),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_valid (grant_valid)
VX_priority_encoder #(
.N (NUM_REQS)
) priority_enc (
.data_in (requests_qual),
.index_out (grant_index),
.onehot_out (grant_onehot),
.valid_out (grant_valid)
);
end

52
hw/rtl/libs/VX_matrix_arbiter.sv
View file

@ -38,57 +38,49 @@ module VX_matrix_arbiter #(
end else begin
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
reg [NUM_REQS-1:1] state [NUM_REQS-1:0];
wire [NUM_REQS-1:0] pri [NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_unqual;
wire [NUM_REQS-1:0] grant;
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = 0; j < NUM_REQS; ++j) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
for (genvar r = 0; r < NUM_REQS; ++r) begin
for (genvar c = 0; c < NUM_REQS; ++c) begin
if (r > c) begin
assign pri[r][c] = requests[c] && state[c][r];
end
else if (j < i) begin
assign pri[j][i] = requests[i] && !state[j][i];
else if (r < c) begin
assign pri[r][c] = requests[c] && !state[r][c];
end
else begin
assign pri[j][i] = 0;
assign pri[r][c] = 0;
end
end
assign grant_unqual[i] = requests[i] && !(| pri[i]);
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
for (genvar j = i + 1; j < NUM_REQS; ++j) begin
for (genvar r = 0; r < NUM_REQS; ++r) begin
assign grant[r] = requests[r] && ~(| pri[r]);
end
for (genvar r = 0; r < NUM_REQS; ++r) begin
for (genvar c = r + 1; c < NUM_REQS; ++c) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= '0;
end else begin
state[i][j] <= (state[i][j] || grant_unqual[j]) && !grant_unqual[i];
state[r][c] <= '0;
end else if (grant_ready) begin
state[r][c] <= (state[r][c] || grant[c]) && ~grant[r];
end
end
end
end
reg [NUM_REQS-1:0] grant_unqual_prev;
always @(posedge clk) begin
if (reset) begin
grant_unqual_prev <= '0;
end else if (grant_ready) begin
grant_unqual_prev <= grant_unqual;
end
end
assign grant_onehot = grant_ready ? grant_unqual : grant_unqual_prev;
assign grant_onehot = grant;
VX_onehot_encoder #(
.N (NUM_REQS)
) encoder (
.data_in (grant_unqual),
.data_out (grant_index),
`UNUSED_PIN (valid_out)
.data_in (grant_onehot),
.data_out (grant_index),
.valid_out (grant_valid)
);
assign grant_valid = (| requests);
end
endmodule

4
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -416,14 +416,12 @@ module VX_rr_arbiter #(
end
end
assign grant_valid = (| requests);
VX_onehot_encoder #(
.N (NUM_REQS)
) onehot_encoder (
.data_in (grant_onehot),
.data_out (grant_index),
`UNUSED_PIN (valid_out)
.valid_out(grant_valid)
);
end else begin