cache bindings and memory perf refactory

This commit is contained in:
Blaise Tine 2023-11-03 08:18:18 -04:00
parent 69f9ae778d
commit c9e6518e05
20 changed files with 746 additions and 1025 deletions

View file

@ -47,10 +47,12 @@ typedef void* vx_device_h;
#define VX_ISA_STD_Q (1ull << 16)
#define VX_ISA_STD_S (1ull << 18)
#define VX_ISA_STD_U (1ull << 20)
#define VX_ISA_BASE(flags) (1 << (((flags >> 30) & 0x3) + 4))
#define VX_ISA_EXT_TEX (1ull << 32)
#define VX_ISA_EXT_RASTER (1ull << 33)
#define VX_ISA_EXT_ROP (1ull << 34)
#define VX_ISA_ARCH(flags) (1 << (((flags >> 30) & 0x3) + 4))
#define VX_ISA_EXT_ICACHE (1ull << 32)
#define VX_ISA_EXT_DCACHE (1ull << 33)
#define VX_ISA_EXT_L2CACHE (1ull << 34)
#define VX_ISA_EXT_L3CACHE (1ull << 35)
#define VX_ISA_EXT_SMEM (1ull << 36)
// device memory types
#define VX_MEM_TYPE_GLOBAL 0