mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
fix quartus build
This commit is contained in:
Blaise Tine
parent
d6255f0445
commit
cb0afd3eec
6 changed files with 67 additions and 80 deletions
|
|
@ -15,7 +15,7 @@ module VX_gpr (
|
|||
`ifndef ASIC
|
||||
assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0);
|
||||
|
||||
byte_enabled_simple_dual_port_ram first_ram(
|
||||
VX_byte_enabled_dual_port_ram be_dp_ram (
|
||||
.we (write_enable),
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
|
|
|||
|
|
@ -1,53 +0,0 @@
|
|||
|
||||
`include "VX_define.vh"
|
||||
|
||||
module byte_enabled_simple_dual_port_ram
|
||||
(
|
||||
input clk;
|
||||
input wire reset;
|
||||
input wire we;
|
||||
input wire[4:0] waddr,
|
||||
input wire[4:0] raddr1,
|
||||
input wire[4:0] raddr2,
|
||||
input wire[`NUM_THREADS-1:0] be,
|
||||
input wire[`NUM_THREADS-1:0][31:0] wdata,
|
||||
output reg[`NUM_THREADS-1:0][31:0] q1
|
||||
output reg[`NUM_THREADS-1:0][31:0] q2
|
||||
);
|
||||
// integer regi;
|
||||
// integer threadi;
|
||||
|
||||
// Thread Byte Bit
|
||||
logic [`NUM_THREADS-1:0][3:0][7:0] GPR[31:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
//--
|
||||
end else begin
|
||||
if (we) begin
|
||||
integer thread_ind;
|
||||
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
|
||||
if (be[thread_ind]) begin
|
||||
GPR[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
|
||||
GPR[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
|
||||
GPR[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
|
||||
GPR[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
|
||||
end
|
||||
end
|
||||
end
|
||||
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
|
||||
// for (regi = 0; regi <= 31; regi = regi + 1) begin
|
||||
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
|
||||
// if (GPR[regi][threadi] != 0) $display("$%d: %h",regi, GPR[regi][threadi]);
|
||||
// end
|
||||
// end
|
||||
end
|
||||
end
|
||||
|
||||
assign q1 = GPR[raddr1];
|
||||
assign q2 = GPR[raddr2];
|
||||
|
||||
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
|
||||
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
|
||||
|
||||
endmodule
|
||||
51
hw/rtl/libs/VX_byte_enabled_dual_port_ram.v
Normal file
51
hw/rtl/libs/VX_byte_enabled_dual_port_ram.v
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
module VX_byte_enabled_dual_port_ram (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire we,
|
||||
input wire [4:0] waddr,
|
||||
input wire [4:0] raddr1,
|
||||
input wire [4:0] raddr2,
|
||||
input wire [`NUM_THREADS-1:0] be,
|
||||
input wire [`NUM_THREADS-1:0][31:0] wdata,
|
||||
output reg [`NUM_THREADS-1:0][31:0] q1,
|
||||
output reg [`NUM_THREADS-1:0][31:0] q2
|
||||
);
|
||||
// integer regi;
|
||||
// integer threadi;
|
||||
|
||||
// Thread Byte Bit
|
||||
logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
//--
|
||||
end else begin
|
||||
if (we) begin
|
||||
integer thread_ind;
|
||||
for (thread_ind = 0; thread_ind < `NUM_THREADS; thread_ind = thread_ind + 1) begin
|
||||
if (be[thread_ind]) begin
|
||||
ram[waddr][thread_ind][0] <= wdata[thread_ind][7:0];
|
||||
ram[waddr][thread_ind][1] <= wdata[thread_ind][15:8];
|
||||
ram[waddr][thread_ind][2] <= wdata[thread_ind][23:16];
|
||||
ram[waddr][thread_ind][3] <= wdata[thread_ind][31:24];
|
||||
end
|
||||
end
|
||||
end
|
||||
// $display("^^^^^^^^^^^^^^^^^^^^^^^");
|
||||
// for (regi = 0; regi <= 31; regi = regi + 1) begin
|
||||
// for (threadi = 0; threadi < `NUM_THREADS; threadi = threadi + 1) begin
|
||||
// if (ram[regi][threadi] != 0) $display("$%d: %h",regi, ram[regi][threadi]);
|
||||
// end
|
||||
// end
|
||||
end
|
||||
end
|
||||
|
||||
assign q1 = ram[raddr1];
|
||||
assign q2 = ram[raddr2];
|
||||
|
||||
// assign q1 = (raddr1 == waddr && (we)) ? wdata : ram[raddr1];
|
||||
// assign q2 = (raddr2 == waddr && (we)) ? wdata : ram[raddr2];
|
||||
|
||||
endmodule
|
||||
|
|
@ -9,9 +9,9 @@ module VX_mult #(
|
|||
parameter PIPELINE=0,
|
||||
parameter FORCE_LE="NO"
|
||||
) (
|
||||
input clock;
|
||||
input aclr;
|
||||
input clken;
|
||||
input clock,
|
||||
input aclr,
|
||||
input clken,
|
||||
|
||||
input [WIDTHA-1:0] dataa,
|
||||
input [WIDTHB-1:0] datab,
|
||||
|
|
|
|||
4
hw/syn/quartus/cache/Makefile
vendored
4
hw/syn/quartus/cache/Makefile
vendored
|
|
@ -1,6 +1,6 @@
|
|||
PROJECT = VX_cache
|
||||
TOP_LEVEL_ENTITY = VX_cache
|
||||
SRC_FILE = ../../../rtl/cache/VX_cache.v
|
||||
SRC_FILE = VX_cache.v
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
# Part, Family
|
||||
|
|
@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
|
|||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
|
||||
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
|
|
|||
|
|
@ -1,10 +1,8 @@
|
|||
PROJECT = Vortex
|
||||
TOP_LEVEL_ENTITY = Vortex_Socket
|
||||
SRC_FILE = ../../../rtl/Vortex.v
|
||||
TOP_LEVEL_ENTITY = Vortex
|
||||
SRC_FILE = Vortex.v
|
||||
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
|
||||
|
||||
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
|
||||
|
||||
# Part, Family
|
||||
FAMILY = "Arria 10"
|
||||
DEVICE = 10AX115N3F40E2SG
|
||||
|
|
@ -16,7 +14,7 @@ ASM_ARGS =
|
|||
STA_ARGS = --do_report_timing
|
||||
|
||||
# Build targets
|
||||
all: $(PROJECT).sta.rpt $(PROJECT).pow.rpt
|
||||
all: $(PROJECT).sta.rpt
|
||||
|
||||
syn: $(PROJECT).syn.rpt
|
||||
|
||||
|
|
@ -26,38 +24,32 @@ asm: $(PROJECT).asm.rpt
|
|||
|
||||
sta: $(PROJECT).sta.rpt
|
||||
|
||||
pow: $(PROJECT).pow.rpt
|
||||
|
||||
smart: smart.log
|
||||
|
||||
# Target implementations
|
||||
STAMP = echo done >
|
||||
|
||||
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
quartus_syn $(PROJECT) $(SYN_ARGS)
|
||||
$(STAMP) fit.chg
|
||||
|
||||
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
quartus_fit $(PROJECT) $(FIT_ARGS)
|
||||
$(STAMP) asm.chg
|
||||
$(STAMP) sta.chg
|
||||
|
||||
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
quartus_asm $(PROJECT) $(ASM_ARGS)
|
||||
|
||||
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
|
||||
|
||||
$(PROJECT).pow.rpt: smart.log pow.chg $(PROJECT).fit.rpt
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_pow $(PROJECT)
|
||||
quartus_sta $(PROJECT) $(STA_ARGS)
|
||||
|
||||
smart.log: $(PROJECT_FILES)
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
quartus_sh --determine_smart_action $(PROJECT) > smart.log
|
||||
|
||||
# Project initialization
|
||||
$(PROJECT_FILES):
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache"
|
||||
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
|
||||
|
||||
syn.chg:
|
||||
$(STAMP) syn.chg
|
||||
|
|
@ -71,11 +63,8 @@ sta.chg:
|
|||
asm.chg:
|
||||
$(STAMP) asm.chg
|
||||
|
||||
pow.chg:
|
||||
$(STAMP) pow.chg
|
||||
|
||||
program: $(PROJECT).sof
|
||||
$(QUARTUS_ROOT)/quartus/bin/quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
|
||||
|
||||
clean:
|
||||
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue