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tracing refactoring

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This commit is contained in:
Blaise Tine 2024-09-08 14:54:04 -07:00
parent fa11d4c502
commit cc105eaea9
6 changed files with 99 additions and 46 deletions
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85
hw/rtl/VX_gpu_pkg.sv
View file

@ -467,13 +467,43 @@ package VX_gpu_pkg;
case (`INST_SFU_BITS'(op_type))
`INST_SFU_TMC: `TRACE(level, ("TMC"))
`INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN"))
`INST_SFU_SPLIT: begin if (op_args.wctl.is_neg) `TRACE(level, ("SPLIT.N")) else `TRACE(level, ("SPLIT")) end
`INST_SFU_SPLIT: begin
if (op_args.wctl.is_neg) begin
`TRACE(level, ("SPLIT.N"))
end else begin
`TRACE(level, ("SPLIT"))
end
end
`INST_SFU_JOIN: `TRACE(level, ("JOIN"))
`INST_SFU_BAR: `TRACE(level, ("BAR"))
`INST_SFU_PRED: begin if (op_args.wctl.is_neg) `TRACE(level, ("PRED.N")) else `TRACE(level, ("PRED")) end
`INST_SFU_CSRRW: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRWI")) else `TRACE(level, ("CSRRW")) end
`INST_SFU_CSRRS: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRSI")) else `TRACE(level, ("CSRRS")) end
`INST_SFU_CSRRC: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRCI")) else `TRACE(level, ("CSRRC")) end
`INST_SFU_PRED: begin
if (op_args.wctl.is_neg) begin
`TRACE(level, ("PRED.N"))
end else begin
`TRACE(level, ("PRED"))
end
end
`INST_SFU_CSRRW: begin
if (op_args.csr.use_imm) begin
`TRACE(level, ("CSRRWI"))
end else begin
`TRACE(level, ("CSRRW"))
end
end
`INST_SFU_CSRRS: begin
if (op_args.csr.use_imm) begin
`TRACE(level, ("CSRRSI"))
end else begin
`TRACE(level, ("CSRRS"))
end
end
`INST_SFU_CSRRC: begin
if (op_args.csr.use_imm) begin
`TRACE(level, ("CSRRCI"))
end else begin
`TRACE(level, ("CSRRC"))
end
end
default: `TRACE(level, ("?"))
endcase
end
@ -482,60 +512,69 @@ package VX_gpu_pkg;
case (`INST_FPU_BITS'(op_type))
`INST_FPU_ADD: begin
if (op_args.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FSUB.D"))
else
end else begin
`TRACE(level, ("FSUB.S"))
end
end else begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FADD.D"))
else
end else begin
`TRACE(level, ("FADD.S"))
end
end
end
`INST_FPU_MADD: begin
if (op_args.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FMSUB.D"))
else
end else begin
`TRACE(level, ("FMSUB.S"))
end
end else begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FMADD.D"))
else
end else begin
`TRACE(level, ("FMADD.S"))
end
end
end
`INST_FPU_NMADD: begin
if (op_args.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FNMSUB.D"))
else
end else begin
`TRACE(level, ("FNMSUB.S"))
end
end else begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FNMADD.D"))
else
end else begin
`TRACE(level, ("FNMADD.S"))
end
end
end
`INST_FPU_MUL: begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FMUL.D"))
else
end else begin
`TRACE(level, ("FMUL.S"))
end
end
`INST_FPU_DIV: begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FDIV.D"))
else
end else begin
`TRACE(level, ("FDIV.S"))
end
end
`INST_FPU_SQRT: begin
if (op_args.fpu.fmt[0])
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FSQRT.D"))
else
end else begin
`TRACE(level, ("FSQRT.S"))
end
end
`INST_FPU_CMP: begin
if (op_args.fpu.fmt[0]) begin

5
hw/rtl/Vortex.sv
View file

@ -198,10 +198,11 @@ module Vortex import VX_gpu_pkg::*; (
`ifdef DBG_TRACE_MEM
always @(posedge clk) begin
if (mem_req_fire) begin
if (mem_req_rw)
if (mem_req_rw) begin
`TRACE(1, ("%d: MEM Wr Req: addr=0x%0h, tag=0x%0h, byteen=0x%h data=0x%h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data))
else
end else begin
`TRACE(1, ("%d: MEM Rd Req: addr=0x%0h, tag=0x%0h, byteen=0x%h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen))
end
end
if (mem_rsp_fire) begin
`TRACE(1, ("%d: MEM Rd Rsp: tag=0x%0h, data=0x%h\n", $time, mem_rsp_tag, mem_rsp_data))

12
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -672,21 +672,23 @@ module VX_cache_bank #(
`TRACE(2, ("%d: %s mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel))
end
if (core_req_fire) begin
if (core_req_rw)
if (core_req_rw) begin
`TRACE(2, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel))
else
end else begin
`TRACE(2, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel))
end
end
if (crsp_queue_fire) begin
`TRACE(2, ("%d: %s core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsp_queue_tag, crsp_queue_idx, crsp_queue_data, req_uuid_st1))
end
if (mreq_queue_push) begin
if (do_creq_wr_st1 && !WRITEBACK)
if (do_creq_wr_st1 && !WRITEBACK) begin
`TRACE(2, ("%d: %s writethrough: addr=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_byteen, mreq_queue_data, req_uuid_st1))
else if (do_writeback_st1)
end else if (do_writeback_st1) begin
`TRACE(2, ("%d: %s writeback: addr=0x%0h, byteen=0x%h, data=0x%h\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_byteen, mreq_queue_data))
else
end else begin
`TRACE(2, ("%d: %s fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(mreq_queue_addr, BANK_ID), mreq_queue_id, req_uuid_st1))
end
end
end
`endif

23
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -267,32 +267,39 @@ module VX_cache_mshr #(
end else begin
show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire;
end
if (allocate_fire)
if (allocate_fire) begin
`TRACE(3, ("%d: %s allocate: addr=0x%0h, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_prev, allocate_id, lkp_req_uuid))
if (lookup_valid)
end
if (lookup_valid) begin
`TRACE(3, ("%d: %s lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_pending, lkp_req_uuid))
if (finalize_valid)
end
if (finalize_valid) begin
`TRACE(3, ("%d: %s finalize release=%b, pending=%b, prev=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID,
finalize_release, finalize_pending, finalize_prev, finalize_id, fin_req_uuid))
if (fill_valid)
end
if (fill_valid) begin
`TRACE(3, ("%d: %s fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id))
if (dequeue_fire)
end
if (dequeue_fire) begin
`TRACE(3, ("%d: %s dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID,
`CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid))
end
if (show_table) begin
`TRACE(3, ("%d: %s table", $time, INSTANCE_ID))
for (integer i = 0; i < MSHR_SIZE; ++i) begin
if (valid_table[i]) begin
`TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID)))
if (write_table[i])
if (write_table[i]) begin
`TRACE(3, ("(w)"))
else
end else begin
`TRACE(3, ("(r)"))
if (next_table[i])
end
if (next_table[i]) begin
`TRACE(3, ("->%0d", next_index[i]))
end
end
end
`TRACE(3, ("\n"))

10
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -159,15 +159,17 @@ module VX_cache_tags #(
end
if (lookup && ~stall) begin
if (tag_matches != 0) begin
if (write)
if (write) begin
`TRACE(3, ("%d: %s write-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), tag_matches, line_sel, line_tag, req_uuid))
else
end else begin
`TRACE(3, ("%d: %s read-hit: addr=0x%0h, way=%b, blk_addr=%0d, tag_id=0x%0h (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), tag_matches, line_sel, line_tag, req_uuid))
end
end else begin
if (write)
if (write) begin
`TRACE(3, ("%d: %s write-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid))
else
end else begin
`TRACE(3, ("%d: %s read-miss: addr=0x%0h, blk_addr=%0d, tag_id=0x%0h, (#%0d)\n", $time, INSTANCE_ID, `CS_LINE_TO_FULL_ADDR(line_addr, BANK_ID), line_sel, line_tag, req_uuid))
end
end
end
end

10
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -233,10 +233,11 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
always @(posedge clk) begin
if (core_req_fire) begin
if (core_bus_if[i].req_data.rw)
if (core_bus_if[i].req_data.rw) begin
`TRACE(1, ("%d: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_bus_if[i].req_data.byteen, core_bus_if[i].req_data.data, core_req_uuid))
else
end else begin
`TRACE(1, ("%d: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag, i, core_req_uuid))
end
end
if (core_rsp_fire) begin
`TRACE(1, ("%d: %s core-rd-rsp: tag=0x%0h, req_idx=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, core_bus_if[i].rsp_data.tag, i, core_bus_if[i].rsp_data.data, core_rsp_uuid))
@ -260,12 +261,13 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
always @(posedge clk) begin
if (mem_req_fire) begin
if (mem_bus_if.req_data.rw)
if (mem_bus_if.req_data.rw) begin
`TRACE(1, ("%d: %s mem-wr-req: addr=0x%0h, tag=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n",
$time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_bus_if.req_data.byteen, mem_bus_if.req_data.data, mem_req_uuid))
else
end else begin
`TRACE(1, ("%d: %s mem-rd-req: addr=0x%0h, tag=0x%0h (#%0d)\n",
$time, INSTANCE_ID, `TO_FULL_ADDR(mem_bus_if.req_data.addr), mem_bus_if.req_data.tag, mem_req_uuid))
end
end
if (mem_rsp_fire) begin
`TRACE(1, ("%d: %s mem-rd-rsp: tag=0x%0h, data=0x%h (#%0d)\n",