mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
90fa9eee7d
commit
cc259f60f6
7 changed files with 32 additions and 29 deletions
14
.travis.yml
14
.travis.yml
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@ -30,25 +30,25 @@ jobs:
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include:
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- stage: test
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name: coverage
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script: cp -r $PWD ../build1 && cd ../build1 && ./ci/regression.sh -coverage
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script: cp -r $PWD ../build1 && cd ../build1 && ./ci/travis_run.py ./ci/regression.sh -coverage
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- stage: test
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name: cluster
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script: cp -r $PWD ../build2 && cd ../build2 && ./ci/regression.sh -cluster
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script: cp -r $PWD ../build2 && cd ../build2 && ./ci/travis_run.py ./ci/regression.sh -cluster
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- stage: test
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name: debug
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script: cp -r $PWD ../build3 && cd ../build3 && ./ci/regression.sh -debug
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script: cp -r $PWD ../build3 && cd ../build3 && ./ci/travis_run.py ./ci/regression.sh -debug
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- stage: test
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name: config
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script: cp -r $PWD ../build4 && cd ../build4 && ./ci/regression.sh -config
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script: cp -r $PWD ../build4 && cd ../build4 && ./ci/travis_run.py ./ci/regression.sh -config
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- stage: test
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name: stress1
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script: cp -r $PWD ../build5 && cd ../build5 && ./ci/regression.sh -stress1
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script: cp -r $PWD ../build5 && cd ../build5 && ./ci/travis_run.py ./ci/regression.sh -stress1
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- stage: test
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name: stress2
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script: cp -r $PWD ../build6 && cd ../build6 && ./ci/regression.sh -stress2
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script: cp -r $PWD ../build6 && cd ../build6 && ./ci/travis_run.py ./ci/regression.sh -stress2
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- stage: test
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name: compiler
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script: cp -r $PWD ../build7 && cd ../build7 && ./ci/test_compiler.sh
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script: cp -r $PWD ../build7 && cd ../build7 && ./ci/travis_run.py /ci/test_compiler.sh
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after_success:
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# Gather code coverage
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@ -27,17 +27,17 @@ cluster()
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echo "begin clustering tests..."
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# warp/threads configurations
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo
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./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=2 --threads=8 --app=demo
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./ci/blackbox.sh --driver=rtlsim --cores=1 --warps=8 --threads=2 --app=demo
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# cores clustering
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=1 --clusters=1 --app=demo --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
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# L2/L3
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=demo --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1"
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echo "clustering tests done!"
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}
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@ -46,9 +46,9 @@ debug()
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{
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echo "begin debugging tests..."
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./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1"
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./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1"
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./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1"
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./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1"
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./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=basic --args="-t0 -n1"
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echo "debugging tests done!"
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}
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@ -106,7 +106,7 @@ stress1()
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{
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echo "begin stress tests..."
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256"
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./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm --args="-n256"
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echo "stress tests done!"
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}
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@ -115,7 +115,7 @@ stress2()
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{
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echo "begin stress tests..."
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./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --clusters=2 --l3cache --app=sgemm --args="-n256"
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echo "stress tests done!"
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}
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@ -148,6 +148,7 @@ module VX_cluster #(
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.DATA_WIDTH (`L2MEM_DATA_WIDTH),
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.ADDR_WIDTH (`L2MEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`XMEM_TAG_WIDTH),
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.TAG_SEL_IDX (1), // Skip 0 for NC flag
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (1)
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) mem_arb (
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@ -306,7 +306,7 @@ module VX_lsu_unit #(
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifndef SYNTHESIS
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + 64 + 1)-1:0] pending_reqs;
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + `NR_BITS + 64 + 1)-1:0] pending_reqs;
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wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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@ -314,7 +314,7 @@ module VX_lsu_unit #(
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pending_reqs <= '0;
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end begin
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if (mbuf_push) begin
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pending_reqs[mbuf_waddr] <= {req_wid, req_pc, $time, 1'b1};
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pending_reqs[mbuf_waddr] <= {req_wid, req_pc, req_rd, $time, 1'b1};
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end
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if (mbuf_pop) begin
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pending_reqs[mbuf_raddr] <= '0;
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@ -324,7 +324,8 @@ module VX_lsu_unit #(
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for (integer i = 0; i < `LSUQ_SIZE; ++i) begin
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if (pending_reqs[i][0]) begin
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assert(($time - pending_reqs[i][1 +: 64]) < delay_timeout) else
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$error("%t: *** D$%0d response timeout: wid=%0d, PC=%0h", $time, CORE_ID, pending_reqs[i][1+64+32 +: `NW_BITS], pending_reqs[i][1+64 +: 32]);
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$error("%t: *** D$%0d response timeout: remaining=%b, wid=%0d, PC=%0h, rd=%0d", $time, CORE_ID,
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rsp_rem_mask[i], pending_reqs[i][1+64+32+`NR_BITS +: `NW_BITS], pending_reqs[i][1+64+`NR_BITS +: 32], pending_reqs[i][1+64 +: `NR_BITS]);
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end
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end
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end
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@ -307,6 +307,7 @@ module VX_mem_unit # (
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.DATA_WIDTH (`DMEM_DATA_WIDTH),
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.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
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.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
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.TAG_SEL_IDX (1), // Skip 0 for NC flag
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.BUFFERED_REQ (1),
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.BUFFERED_RSP (2)
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) mem_arb (
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@ -46,8 +46,10 @@ localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8;
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localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE);
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localparam AVS_RD_QUEUE_SIZE = 4;
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localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH));
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localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH));
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localparam AVS_REQ_TAGW_VX_ = `VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH);
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localparam AVS_REQ_TAGW_VX = `MAX(`VX_MEM_TAG_WIDTH, AVS_REQ_TAGW_VX_);
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localparam AVS_REQ_TAGW_CCI_ = CCI_ADDR_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(CCI_DATA_WIDTH);
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localparam AVS_REQ_TAGW_CCI = `MAX(CCI_ADDR_WIDTH, AVS_REQ_TAGW_CCI_);
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localparam AVS_REQ_TAGW = `MAX(AVS_REQ_TAGW_VX, AVS_REQ_TAGW_CCI);
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localparam CCI_RD_WINDOW_SIZE = 8;
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@ -111,9 +111,9 @@
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"!cci_pending_writes_full": 1,
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"?afu_mem_req_fire": 1,
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"afu_mem_req_addr": 26,
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"afu_mem_req_tag": 29,
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"afu_mem_req_tag": 32,
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"?afu_mem_rsp_fire": 1,
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"afu_mem_rsp_tag": 29
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"afu_mem_rsp_tag": 32
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},
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"afu/vortex": {
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"!reset": 1,
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@ -203,9 +203,7 @@
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"is_fill_st0": 1,
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"is_mshr_st0": 1,
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"miss_st0": 1,
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"force_miss_st0": 1,
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"mshr_push": 1,
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"?crsq_in_stall": 1,
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"?crsq_stall": 1,
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"?mreq_alm_full": 1,
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"?mshr_alm_full": 1
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}
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