mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
cache data access with decoupled read/write ports
This commit is contained in:
Blaise Tine
parent
3e961c4e6e
commit
ccb74ef286
2 changed files with 107 additions and 78 deletions
139
hw/rtl/cache/VX_bank.v
vendored
139
hw/rtl/cache/VX_bank.v
vendored
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@ -154,14 +154,15 @@ module VX_bank #(
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1;
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wire [NUM_PORTS-1:0] pmask_st0, pmask_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] rdata_st1;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] rdata_st0, rdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [CORE_TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire valid_st0, valid_st1;
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wire is_fill_st0, is_fill_st1;
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wire is_mshr_st0, is_mshr_st1;
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wire miss_st0, miss_st1;
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wire prev_miss_dep_st0, prev_miss_dep_st1;
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wire prev_miss_dep_st0;
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wire fill_req_unqual_st0, fill_req_unqual_st1;
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wire force_miss_st0, force_miss_st1;
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wire writeen_unqual_st0, writeen_unqual_st1;
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wire incoming_fill_st0, incoming_fill_st1;
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@ -218,7 +219,7 @@ module VX_bank #(
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wire [`CACHE_LINE_WIDTH-1:0] creq_line_data;
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if (`WORD_SELECT_BITS != 0) begin
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if (`WORDS_PER_LINE > 1) begin
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if (NUM_PORTS > 1) begin
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reg [`CACHE_LINE_WIDTH-1:0] creq_line_data_r;
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always @(*) begin
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@ -278,7 +279,7 @@ module VX_bank #(
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end
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`endif
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wire tag_match;
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wire tag_match_st0;
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VX_tag_access #(
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.BANK_ID (BANK_ID),
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@ -289,49 +290,88 @@ module VX_bank #(
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.WORD_SIZE (WORD_SIZE),
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.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET)
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) tag_access (
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.clk (clk),
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.reset (reset),
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.clk (clk),
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.reset (reset),
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`ifdef DBG_CACHE_REQ_INFO
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.debug_pc (debug_pc_st0),
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.debug_wid (debug_wid_st0),
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.debug_pc (debug_pc_st0),
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.debug_wid (debug_wid_st0),
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`endif
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// read/Fill
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.lookup (valid_st0 && !is_fill_st0),
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.addr (addr_st0),
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.fill (valid_st0 && is_fill_st0),
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.is_flush (is_flush_st0),
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.tag_match (tag_match)
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.lookup (valid_st0 && !is_fill_st0),
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.addr (addr_st0),
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.fill (valid_st0 && is_fill_st0),
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.is_flush (is_flush_st0),
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.tag_match (tag_match_st0)
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);
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// redundant fills
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wire is_redundant_fill = !IN_ORDER_DRAM && is_fill_st0 && tag_match;
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wire is_redundant_fill_st0 = !IN_ORDER_DRAM && is_fill_st0 && tag_match_st0;
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// we had a miss with prior request for the current address
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assign prev_miss_dep_st0 = is_miss_st1 && (addr_st0 == addr_st1);
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assign miss_st0 = !is_fill_st0 && !tag_match;
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assign miss_st0 = !is_fill_st0 && !tag_match_st0;
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// force miss to ensure commit order when a new request has pending previous requests to same block
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// also force a miss for mshr requests when previous requests got a miss
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assign force_miss_st0 = (!is_fill_st0 && !is_mshr_st0 && (mshr_pending_st0 || prev_miss_dep_st0))
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|| (is_mshr_st0 && is_miss_st1 && is_mshr_st1);
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|| (is_mshr_st0 && is_mshr_st1 && is_miss_st1);
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assign writeen_unqual_st0 = (!is_fill_st0 && tag_match && mem_rw_st0)
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|| (is_fill_st0 && !is_redundant_fill);
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assign writeen_unqual_st0 = (WRITE_ENABLE && !is_fill_st0 && tag_match_st0 && mem_rw_st0)
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|| (is_fill_st0 && !is_redundant_fill_st0);
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assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr_qual);
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assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_DRAM && is_mshr_st0 && !prev_miss_dep_st0));
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wire [`CACHE_LINE_WIDTH-1:0] rdata_unqual;
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wire writeen_st1 = writeen_unqual_st1 && (is_fill_st1 || !force_miss_st1);
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wire rw_hazard = valid_st1 && writeen_st1 && (addr_st0 == addr_st1)
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&& ((`WORDS_PER_LINE == 1) || (is_fill_st1 || (wsel_st0 == wsel_st1)));
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if (`WORDS_PER_LINE > 1) begin
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for (genvar p = 0; p < NUM_PORTS; p++) begin
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reg [`WORD_WIDTH-1:0] read_data_r;
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wire [`WORD_WIDTH-1:0] write_data = wdata_st1[wsel_st0 * `WORD_WIDTH +: `WORD_WIDTH];
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always @(*) begin
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read_data_r = rdata_unqual[wsel_st0[p] * `WORD_WIDTH +: `WORD_WIDTH];
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for (integer i = 0; i < WORD_SIZE; i++) begin
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if (rw_hazard
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&& (is_fill_st1 || (WRITE_ENABLE && byteen_st1[p][i]))
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&& ((NUM_PORTS == 1) || pmask_st1[p])) begin
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read_data_r[i * 8 +: 8] = write_data[i * 8 +: 8];
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end
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end
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end
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assign rdata_st0[p] = read_data_r;
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end
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end else begin
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reg [`WORD_WIDTH-1:0] read_data_r;
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always @(*) begin
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read_data_r = rdata_unqual;
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for (integer i = 0; i < WORD_SIZE; i++) begin
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if (rw_hazard
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&& (is_fill_st1 || (WRITE_ENABLE && byteen_st1[0][i]))) begin
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read_data_r[i * 8 +: 8] = wdata_st1[i * 8 +: 8];
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end
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end
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end
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assign rdata_st0[0] = read_data_r;
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH),
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`WORD_WIDTH + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, prev_miss_dep_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, prev_miss_dep_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1})
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, fill_req_unqual_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, rdata_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, fill_req_unqual_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, rdata_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1})
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);
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`ifdef DBG_CACHE_REQ_INFO
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@ -342,8 +382,6 @@ module VX_bank #(
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end
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`endif
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wire writeen_st1 = writeen_unqual_st1 && (is_fill_st1 || !force_miss_st1);
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wire crsq_push_st1 = !is_fill_st1 && !mem_rw_st1 && !miss_st1 && !force_miss_st1;
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wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1);
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@ -351,28 +389,21 @@ module VX_bank #(
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wire incoming_fill_qual_st1 = (dram_rsp_valid && (addr_st1 == dram_rsp_addr_qual))
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|| incoming_fill_st1;
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wire send_fill_req_st1 = !is_fill_st1 && !mem_rw_st1 && miss_st1
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&& (!force_miss_st1 || (!IN_ORDER_DRAM && is_mshr_st1 && !prev_miss_dep_st1))
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&& !incoming_fill_qual_st1;
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wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1;
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wire dreq_push_st1 = send_fill_req_st1 || do_writeback_st1;
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wire dreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1)
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|| do_writeback_st1;
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wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1;
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if (`WORD_SELECT_BITS != 0) begin
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if (`WORDS_PER_LINE > 1) begin
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reg [CACHE_LINE_SIZE-1:0] line_byteen_r;
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always @(*) begin
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line_byteen_r = 0;
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if (NUM_PORTS > 1) begin
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if (pmask_st1[p]) begin
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line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
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end
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if ((NUM_PORTS == 1) || pmask_st1[p]) begin
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line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
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end
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end else begin
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line_byteen_r[wsel_st1[0] * WORD_SIZE +: WORD_SIZE] = byteen_st1[0];
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end
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end
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assign line_byteen_st1 = line_byteen_r;
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@ -393,21 +424,23 @@ module VX_bank #(
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.reset (reset),
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`ifdef DBG_CACHE_REQ_INFO
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.debug_pc (debug_pc_st1),
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.debug_wid (debug_wid_st1),
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.debug_pc_r (debug_pc_st0),
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.debug_wid_r (debug_wid_st0),
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.debug_pc_w (debug_pc_st1),
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.debug_wid_w (debug_wid_st1),
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`endif
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.addr (addr_st1),
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// reading
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.readen (valid_st1 && !mem_rw_st1 && !is_fill_st1),
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.rddata (rdata_st1),
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.readen (valid_st0 && !is_fill_st0 && !mem_rw_st0),
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.raddr (addr_st0),
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.rdata (rdata_unqual),
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// writing
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.writeen (valid_st1 && writeen_st1),
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.is_fill (is_fill_st1),
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.byteen (line_byteen_st1),
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.wrdata (wdata_st1)
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.waddr (addr_st1),
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.wdata (wdata_st1)
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);
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assign mshr_push = valid_st1 && mshr_push_st1;
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@ -477,20 +510,12 @@ module VX_bank #(
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wire [CORE_TAG_WIDTH-1:0] crsq_tag;
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wire crsq_empty;
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assign crsq_push = valid_st1 && crsq_push_st1;
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assign crsq_pop = core_rsp_valid && core_rsp_ready;
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if (`WORD_SELECT_BITS != 0) begin
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for (genvar p = 0; p < NUM_PORTS; ++p) begin
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assign crsq_data[p] = rdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
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end
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end else begin
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assign crsq_data = rdata_st1;
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end
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assign crsq_push = valid_st1 && crsq_push_st1;
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assign crsq_pop = core_rsp_valid && core_rsp_ready;
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assign crsq_data = rdata_st1;
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assign crsq_pmask = pmask_st1;
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assign crsq_tid = req_tid_st1;
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assign crsq_tag = tag_st1;
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assign crsq_tid = req_tid_st1;
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assign crsq_tag = tag_st1;
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VX_fifo_queue #(
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.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
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46
hw/rtl/cache/VX_data_access.v
vendored
46
hw/rtl/cache/VX_data_access.v
vendored
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@ -12,69 +12,73 @@ module VX_data_access #(
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable write-through
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parameter WRITE_THROUGH = 1
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parameter WRITE_ENABLE = 1
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc,
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input wire[`NW_BITS-1:0] debug_wid,
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input wire[31:0] debug_pc_r,
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input wire[`NW_BITS-1:0] debug_wid_r,
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input wire[31:0] debug_pc_w,
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input wire[`NW_BITS-1:0] debug_wid_w,
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`IGNORE_WARNINGS_END
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`endif
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] addr,
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`IGNORE_WARNINGS_END
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// reading
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input wire readen,
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output wire [`CACHE_LINE_WIDTH-1:0] rddata,
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] raddr,
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`IGNORE_WARNINGS_END
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output wire [`CACHE_LINE_WIDTH-1:0] rdata,
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// writing
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input wire writeen,
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input wire is_fill,
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input wire [CACHE_LINE_SIZE-1:0] byteen,
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input wire [`CACHE_LINE_WIDTH-1:0] wrdata
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] waddr,
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`IGNORE_WARNINGS_END
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input wire [`CACHE_LINE_WIDTH-1:0] wdata
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);
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`UNUSED_VAR (reset)
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`UNUSED_VAR (readen)
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wire [`LINE_SELECT_BITS-1:0] line_addr;
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wire [`LINE_SELECT_BITS-1:0] line_raddr, line_waddr;
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wire [CACHE_LINE_SIZE-1:0] byte_enable;
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assign line_addr = addr[`LINE_SELECT_BITS-1:0];
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
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assign line_raddr = raddr[`LINE_SELECT_BITS-1:0];
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assign line_waddr = waddr[`LINE_SELECT_BITS-1:0];
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assign byte_enable = (WRITE_ENABLE && !is_fill) ? byteen : {CACHE_LINE_SIZE{1'b1}};
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VX_sp_ram #(
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VX_dp_ram #(
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.DATAW(CACHE_LINE_SIZE * 8),
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.SIZE(`LINES_PER_BANK),
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.BYTEENW(CACHE_LINE_SIZE),
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.RWCHECK(1)
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) data_store (
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.clk(clk),
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.addr(line_addr),
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.raddr(line_raddr),
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.waddr(line_waddr),
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.wren(writeen),
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.byteen(byte_enable),
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.rden(1'b1),
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.din(wrdata),
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.dout(rddata)
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.din(wdata),
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.dout(rdata)
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);
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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if (writeen) begin
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if (is_fill) begin
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$display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wrdata);
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$display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr, BANK_ID), line_waddr, wdata);
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end else begin
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wrdata);
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr, BANK_ID), debug_wid_w, debug_pc_w, byte_enable, line_waddr, wdata);
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end
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end
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if (readen) begin
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$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, rddata);
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$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr, BANK_ID), debug_wid_r, debug_pc_r, line_raddr, rdata);
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end
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end
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`endif
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