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minor improvement

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This commit is contained in:
Blaise Tine 2020-11-03 17:08:26 -08:00
parent 323d2a3b3e
commit cd8ce20bd6
2 changed files with 5 additions and 5 deletions
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6
hw/rtl/cache/VX_bank.v vendored
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@ -339,7 +339,7 @@ module VX_bank #(
reqq_pop_unqual ? reqq_req_writeword_st0 :
0;
// we have a miss in msrq or going into it for the current address
// we have a miss in msrq or in stage 2 for the current address
wire msrq_pending_hazard_st0 = msrq_pending_hazard_unqual_st0
|| (miss_add_unqual && (addr_st2 == addr_st0));
@ -486,7 +486,7 @@ module VX_bank #(
assign is_msrq_miss_st2 = miss_add_unqual && is_msrq_st2;
// a matching incoming fill request to the block is in stage 0
wire incoming_st0_fill_st2 = is_fill_st0 && (addr_st2 == addr_st0);
wire incoming_st0_fill_st2 = is_fill_st0 && (addr_st2 == dfpq_addr_st0);
// a matching incoming fill request to the block is in stage 1
wire incoming_st1_fill_st2 = is_fill_st1 && (addr_st2 == addr_st1);
@ -554,7 +554,7 @@ module VX_bank #(
// fill
.update_ready_st0 (update_ready_st0),
.fill_addr_st0 (addr_st0),
.addr_st0 (addr_st0),
.pending_hazard_st0 (msrq_pending_hazard_unqual_st0),
// dequeue

4
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View file

@ -56,7 +56,7 @@ module VX_cache_miss_resrv #(
// fill
input wire update_ready_st0,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st0,
input wire[`LINE_ADDR_WIDTH-1:0] addr_st0,
output wire pending_hazard_st0,
// dequeue
@ -93,7 +93,7 @@ module VX_cache_miss_resrv #(
wire [MRVQ_SIZE-1:0] valid_address_match;
for (genvar i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st0);
assign valid_address_match[i] = valid_table[i] && (addr_table[i] == addr_st0);
end
assign pending_hazard_st0 = (| valid_address_match);