mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
fixed redundant cache fills
This commit is contained in:
Blaise Tine
parent
c39f98a8af
commit
ce95c40aee
3 changed files with 44 additions and 31 deletions
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@ -56,7 +56,7 @@ VL_FLAGS += verilator.vlt
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += -DVCD_OUTPUT --assert --trace --trace-structs --trace-threads 1 $(DBG_FLAGS)
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VL_FLAGS += -DVCD_OUTPUT --assert --trace --trace-structs $(DBG_FLAGS)
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CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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55
hw/rtl/cache/VX_bank.v
vendored
55
hw/rtl/cache/VX_bank.v
vendored
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@ -528,24 +528,38 @@ module VX_bank #(
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wire [`WORD_WIDTH-1:0] writeword_st3;
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wire [`WORD_WIDTH-1:0] readword_st3;
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wire [`BANK_LINE_WIDTH-1:0] readdata_st3;
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wire dirty_st3;
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wire [BANK_LINE_SIZE-1:0] dirtyb_st3;
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wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st3;
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wire [`TAG_SELECT_BITS-1:0] readtag_st3;
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wire is_fill_st3;
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wire [`TAG_SELECT_BITS-1:0] readtag_st3;
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wire is_snp_st3;
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wire snp_invalidate_st3;
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wire is_msrq_st3;
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wire send_core_rsp_st3;
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wire send_fill_req_st3;
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wire do_writeback_st3;
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wire send_snp_rsp_st3;
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wire send_core_rsp_st2 = valid_st2 && !is_fill_st2 && !is_snp_st2 && !miss_st2 && !force_miss_st2;
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wire send_fill_req_st2 = valid_st2 && miss_st2
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&& (!force_miss_st2
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|| (is_msrq_st2 && addr_st2 != addr_st3));
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wire do_writeback_st2 = valid_st2 && dirty_st2
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&& (is_fill_st2
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|| (!force_miss_st2 && is_snp_st2));
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wire send_snp_rsp_st2 = valid_st2 && is_snp_st2 && !force_miss_st2;
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VX_generic_register #(
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.N(1+ 1+ 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
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.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
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) pipe_reg2 (
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.clk (clk),
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.reset (reset),
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.stall (pipeline_stall),
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.flush (1'b0),
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.in ({is_msrq_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, is_fill_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirty_st2, dirtyb_st2, inst_meta_st2}),
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.out ({is_msrq_st3, force_miss_st3, is_snp_st3, snp_invalidate_st3, is_fill_st3, valid_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirty_st3, dirtyb_st3, inst_meta_st3})
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.in ({is_msrq_st2, send_core_rsp_st2, send_fill_req_st2, do_writeback_st2, send_snp_rsp_st2, force_miss_st2, is_snp_st2, snp_invalidate_st2, valid_st2, addr_st2, wsel_st2, writeword_st2, readword_st2, readdata_st2, readtag_st2, miss_st2, dirtyb_st2, inst_meta_st2}),
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.out ({is_msrq_st3, send_core_rsp_st3, send_fill_req_st3, do_writeback_st3, send_snp_rsp_st3, force_miss_st3, is_snp_st3, snp_invalidate_st3, valid_st3, addr_st3, wsel_st3, writeword_st3, readword_st3, readdata_st3, readtag_st3, miss_st3, dirtyb_st3, inst_meta_st3})
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);
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`ifdef DBG_CORE_REQ_INFO
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@ -592,8 +606,7 @@ module VX_bank #(
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// push missed requests as 'ready' is this was a forced missed
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// this request will be queued behind prior requests so will only pop when the fill arrives.
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wire msrq_init_ready_state_st3 = !miss_st3
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|| incoming_fill;
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wire msrq_init_ready_state_st3 = !miss_st3 || incoming_fill;
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VX_cache_miss_resrv #(
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.BANK_ID (BANK_ID),
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@ -657,11 +670,13 @@ module VX_bank #(
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.dequeue_st3 (msrq_dequeue_st3)
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);
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end else begin
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`UNUSED_VAR (valid_st3)
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`UNUSED_VAR (msrq_push)
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`UNUSED_VAR (wsel_st3)
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`UNUSED_VAR (writeword_st3)
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`UNUSED_VAR (snp_invalidate_st3)
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`UNUSED_VAR (req_byteen_st3)
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`UNUSED_VAR (is_snp_st3)
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assign msrq_pending_hazard_unqual_st0 = 0;
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assign msrq_full = 0;
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assign msrq_almfull = 0;
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@ -681,7 +696,7 @@ module VX_bank #(
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wire cwbq_empty, cwbq_full;
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wire cwbq_push_unqual = valid_st3 && !is_fill_st3 && !is_snp_st3 && !miss_st3 && !force_miss_st3 && !req_rw_st3;
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wire cwbq_push_unqual = send_core_rsp_st3 && !req_rw_st3;
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assign cwbq_push_stall = cwbq_push_unqual && cwbq_full;
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wire cwbq_push = cwbq_push_unqual
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@ -717,14 +732,12 @@ module VX_bank #(
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wire dwbq_empty, dwbq_full;
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wire dwbq_is_fill = valid_st3 && miss_st3 && (!force_miss_st3 || is_msrq_st3);
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wire dwbq_is_wb = valid_st3 && dirty_st3 && (is_fill_st3 || (!force_miss_st3 && is_snp_st3));
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wire dwbq_push_unqual = dwbq_is_fill || dwbq_is_wb;
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wire dwbq_push_unqual = send_fill_req_st3 || do_writeback_st3;
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assign dwbq_push_stall = dwbq_push_unqual && dwbq_full;
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wire dwbq_push = dwbq_push_unqual
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&& !(dwbq_is_fill && incoming_fill) // not in 'dwbq_push_stall' to reduce clock delay
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&& !(send_fill_req_st3 && incoming_fill) // not in 'dwbq_push_stall' to reduce clock delay
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&& !dwbq_full
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&& !msrq_push_stall
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&& !cwbq_push_stall
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@ -732,10 +745,10 @@ module VX_bank #(
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wire dwbq_pop = dram_req_valid && dram_req_ready;
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wire [`LINE_ADDR_WIDTH-1:0] dwbq_addr = dwbq_is_wb ? {readtag_st3, addr_st3[`LINE_SELECT_BITS-1:0]} :
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addr_st3;
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wire [`LINE_ADDR_WIDTH-1:0] dwbq_addr = do_writeback_st3 ? {readtag_st3, addr_st3[`LINE_SELECT_BITS-1:0]} :
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addr_st3;
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wire [BANK_LINE_SIZE-1:0] dwbq_byteen = dwbq_is_wb ? dirtyb_st3 : {BANK_LINE_SIZE{1'b1}};
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wire [BANK_LINE_SIZE-1:0] dwbq_byteen = do_writeback_st3 ? dirtyb_st3 : {BANK_LINE_SIZE{1'b1}};
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if (DRAM_ENABLE) begin
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VX_generic_queue #(
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@ -746,8 +759,8 @@ module VX_bank #(
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.reset (reset),
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.push (dwbq_push),
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.pop (dwbq_pop),
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.data_in ({dwbq_is_wb, dwbq_byteen, dwbq_addr, readdata_st3}),
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.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
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.data_in ({do_writeback_st3, dwbq_byteen, dwbq_addr, readdata_st3}),
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.data_out({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
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.empty (dwbq_empty),
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.full (dwbq_full),
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`UNUSED_PIN (size)
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@ -775,7 +788,7 @@ module VX_bank #(
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wire snpq_empty, snpq_full;
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wire snpq_push_unqual = valid_st3 && is_snp_st3 && !force_miss_st3;
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wire snpq_push_unqual = send_snp_rsp_st3;
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assign snpq_push_stall = snpq_push_unqual && snpq_full;
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@ -815,7 +828,7 @@ module VX_bank #(
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end
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assign snp_rsp_valid = !snpq_empty
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&& dwbq_empty; // ensure all writebacks are sent
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&& dwbq_empty; // ensure all writebacks are sent
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// bank pipeline stall
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assign pipeline_stall = msrq_push_stall
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@ -861,7 +874,7 @@ module VX_bank #(
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$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), cwbq_tag_st3, cwbq_tid_st3, cwbq_data_st3, debug_wid_st3, debug_pc_st3);
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end
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if (dwbq_push) begin
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if (dwbq_is_wb)
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if (do_writeback_st3)
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$display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dwbq_addr, BANK_ID), readdata_st3, dirtyb_st3, debug_wid_st3, debug_pc_st3);
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else
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$display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dwbq_addr, BANK_ID), debug_wid_st3, debug_pc_st3);
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18
hw/rtl/cache/VX_tag_access.v
vendored
18
hw/rtl/cache/VX_tag_access.v
vendored
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@ -99,15 +99,15 @@ module VX_tag_access #(
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&& !tags_match;
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assign use_do_write = valid_in
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&& is_write_in
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&& use_read_valid
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&& !core_req_miss
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&& !force_miss_in
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&& !stall;
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&& is_write_in
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&& use_read_valid
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&& !core_req_miss
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&& !force_miss_in
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&& !stall;
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assign use_do_fill = valid_in
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&& is_fill_in
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&& !stall;
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&& is_fill_in
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&& !stall;
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assign use_invalidate = valid_in
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&& is_snp_in
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@ -117,8 +117,7 @@ module VX_tag_access #(
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&& !stall;
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assign miss_out = core_req_miss;
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assign dirty_out = valid_in && use_read_valid && use_read_dirty
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&& !(is_fill_in && tags_match); // disable writeback for redundant fills
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assign dirty_out = valid_in && use_read_valid && use_read_dirty;
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assign readtag_out = use_read_tag;
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assign writeen_out = (use_do_write || use_do_fill);
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@ -128,6 +127,7 @@ module VX_tag_access #(
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if (valid_in && !stall) begin
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if (use_do_fill && tags_match) begin
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$display("%t: warning: redundant fill - addr=%0h", $time, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID));
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assert(0);
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end
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if (use_do_fill) begin
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$display("%t: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h, old_tag_id=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_in, BANK_ID), addrline, addrtag, qual_read_tag);
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