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rtl refactoring

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This commit is contained in:
Blaise Tine 2020-05-20 16:59:14 -04:00
parent b5569dd525
commit cefd0d85af
11 changed files with 59 additions and 55 deletions
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6
driver/rtlsim/Makefile
View file

@ -5,11 +5,11 @@ CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
# control RTL debug print states
DBG_PRINT = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_CORE_DCACHE \
-DDBG_PRINT_CACHE_BANK \
-DDBG_PRINT_CORE_DCACHE \
-DDBG_PRINT_CACHE_BANK \
-DDBG_PRINT_CACHE_SNP \
-DDBG_PRINT_CACHE_MSRQ \
-DDBG_PRINT_DRAM
-DDBG_PRINT_DRAM
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2

4
hw/rtl/VX_define.vh
View file

@ -22,6 +22,10 @@
/* verilator lint_on PINCONNECTEMPTY */ \
/* verilator lint_on DECLFILENAME */
`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \
. x () \
/* verilator lint_on PINCONNECTEMPTY */
`define STRINGIFY(x) `"x`"
`define STATIC_ASSERT(cond, msg) \

54
hw/rtl/VX_dmem_ctrl.v
View file

@ -95,43 +95,41 @@ module VX_dmem_ctrl # (
.core_rsp_tag (smem_core_rsp_if.core_rsp_tag),
.core_rsp_ready (smem_core_rsp_if.core_rsp_ready),
`IGNORE_WARNINGS_BEGIN
// DRAM request
.dram_req_read (),
.dram_req_write (),
.dram_req_addr (),
.dram_req_data (),
.dram_req_tag (),
`UNUSED_PIN(dram_req_read),
`UNUSED_PIN(dram_req_write),
`UNUSED_PIN(dram_req_addr),
`UNUSED_PIN(dram_req_data),
`UNUSED_PIN(dram_req_tag),
.dram_req_ready (1'b0),
// DRAM response
.dram_rsp_valid (1'b0),
.dram_rsp_data (0),
.dram_rsp_tag (`SDRAM_TAG_WIDTH'(0)),
.dram_rsp_ready (),
`UNUSED_PIN(dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_tag (0),
.snp_req_ready (),
`UNUSED_PIN(snp_req_ready),
// Snoop response
.snp_rsp_valid (),
.snp_rsp_tag (),
`UNUSED_PIN(snp_rsp_valid),
`UNUSED_PIN(snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Snoop forward out
.snp_fwdout_valid (),
.snp_fwdout_addr (),
.snp_fwdout_tag (),
`UNUSED_PIN(snp_fwdout_valid),
`UNUSED_PIN(snp_fwdout_addr),
`UNUSED_PIN(snp_fwdout_tag),
.snp_fwdout_ready (0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END
`UNUSED_PIN(snp_fwdin_ready)
);
VX_cache #(
@ -204,18 +202,16 @@ module VX_dmem_ctrl # (
.snp_rsp_tag (dcache_snp_rsp_if.snp_rsp_tag),
.snp_rsp_ready (dcache_snp_rsp_if.snp_rsp_ready),
`IGNORE_WARNINGS_BEGIN
// Snoop forward out
.snp_fwdout_valid (),
.snp_fwdout_addr (),
.snp_fwdout_tag (),
`UNUSED_PIN(snp_fwdout_valid),
`UNUSED_PIN(snp_fwdout_addr),
`UNUSED_PIN(snp_fwdout_tag),
.snp_fwdout_ready (0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END
`UNUSED_PIN(snp_fwdin_ready)
);
VX_cache #(
@ -276,29 +272,27 @@ module VX_dmem_ctrl # (
.dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag),
.dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
`IGNORE_WARNINGS_BEGIN
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_tag (0),
.snp_req_ready (),
`UNUSED_PIN(snp_req_ready),
// Snoop response
.snp_rsp_valid (),
.snp_rsp_tag (),
`UNUSED_PIN(snp_rsp_valid),
`UNUSED_PIN(snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Snoop forward out
.snp_fwdout_valid (),
.snp_fwdout_addr (),
.snp_fwdout_tag (),
`UNUSED_PIN(snp_fwdout_valid),
`UNUSED_PIN(snp_fwdout_addr),
`UNUSED_PIN(snp_fwdout_tag),
.snp_fwdout_ready (0),
// Snoop forward in
.snp_fwdin_valid (0),
.snp_fwdin_tag (0),
.snp_fwdin_ready ()
`IGNORE_WARNINGS_END
`UNUSED_PIN(snp_fwdin_ready)
);
endmodule

6
hw/rtl/VX_gpr.v
View file

@ -72,7 +72,7 @@ module VX_gpr (
for (i = 0; i < 'NT; i=i+4)
begin
`IGNORE_WARNINGS_BEGIN
`IGNORE_WARNINGS_BEGIN
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
@ -109,9 +109,7 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
`IGNORE_WARNINGS_END
`IGNORE_WARNINGS_BEGIN
rf2_`NUM_GPRSx128_wm1 second_ram (
.CENYA(),
.AYA(),
@ -148,7 +146,7 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
`IGNORE_WARNINGS_END
`IGNORE_WARNINGS_END
end
`endif

3
hw/rtl/VX_gpr_stage.v
View file

@ -100,7 +100,8 @@ module VX_gpr_stage (
.stall (stall_rest),
.flush (stall_rest),
.in (stall_lsu),
.out (delayed_lsu_last_cycle)
.out (delayed_lsu_last_cycle),
`UNUSED_PIN(size)
);
wire[`NUM_THREADS-1:0][31:0] temp_store_data;

3
hw/rtl/VX_lsu_addr_gen.v
View file

@ -3,8 +3,7 @@
module VX_lsu_addr_gen (
input wire[`NUM_THREADS-1:0][31:0] base_address,
input wire[31:0] offset,
output wire[`NUM_THREADS-1:0][31:0] address
output wire[`NUM_THREADS-1:0][31:0] address
);
genvar i;
generate

14
hw/rtl/cache/VX_bank.v vendored
View file

@ -150,7 +150,8 @@ module VX_bank #(
.pop (snrq_pop),
.data_out({snrq_addr_st0, snrq_tag_st0}),
.empty (snrq_empty),
.full (snrq_full)
.full (snrq_full),
`UNUSED_PIN(size)
);
assign snp_req_ready = ~snrq_full;
@ -172,7 +173,8 @@ module VX_bank #(
.pop (dfpq_pop),
.data_out({dfpq_addr_st0, dfpq_filldata_st0}),
.empty (dfpq_empty),
.full (dfpq_full)
.full (dfpq_full),
`UNUSED_PIN(size)
);
assign dram_fill_rsp_ready = !dfpq_full;
@ -467,7 +469,7 @@ module VX_bank #(
.stall(stall_bank_pipe),
.flush(1'b0),
.in ({mrvq_init_ready_state_st1e, snp_to_mrvq_st1e, is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
.out ({mrvq_init_ready_state_unqual_st2, snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
@ -582,7 +584,8 @@ module VX_bank #(
.pop (cwbq_pop),
.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
.empty (cwbq_empty),
.full (cwbq_full)
.full (cwbq_full),
`UNUSED_PIN(size)
);
assign core_rsp_valid = !cwbq_empty;
@ -651,7 +654,8 @@ module VX_bank #(
.pop (dwbq_pop),
.data_out({dwbq_is_dwb_out, dwbq_is_snp_out, dram_wb_req_addr, dram_wb_req_data, snp_rsp_tag}),
.empty (dwbq_empty),
.full (dwbq_full)
.full (dwbq_full),
`UNUSED_PIN(size)
);
wire dram_wb_req_fire = dram_wb_req_valid && dram_wb_req_ready;

3
hw/rtl/cache/VX_cache_dfq_queue.v vendored
View file

@ -50,7 +50,8 @@ module VX_cache_dfq_queue #(
.pop (pop_qual),
.data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
.empty (o_empty),
.full (dfqq_full)
.full (dfqq_full),
`UNUSED_PIN(size)
);
assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}});

15
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View file

@ -77,7 +77,7 @@ module VX_cache_miss_resrv #(
reg [MRVQ_SIZE-1:0] valid_address_match;
genvar i;
generate
generate
for (i = 0; i < MRVQ_SIZE; i++) begin
assign valid_address_match[i] = valid_table[i] && (addr_table[i] === fill_addr_st1);
assign make_ready[i] = is_fill_st1 && valid_address_match[i];
@ -143,16 +143,17 @@ module VX_cache_miss_resrv #(
end
end
`ifdef DBG_PRINT_CACHE_MSRQ
`ifdef DBG_PRINT_CACHE_MSRQ
integer j;
always_ff @(posedge clk) begin
if (mrvq_push || mrvq_pop) begin
$write("%t: bank%02d:%01d msrq: push=%b pop=%b", $time, CACHE_ID, BANK_ID, mrvq_push, mrvq_pop);
for (int i = 0; i < MRVQ_SIZE; i++) begin
if (valid_table[i]) begin
for (j = 0; j < MRVQ_SIZE; j++) begin
if (valid_table[j]) begin
$write(" ");
if (i == head_ptr) $write("*");
if (~ready_table[i]) $write("!");
$write("addr%0d=%0h", i, `LINE_TO_BYTE_ADDR(addr_table[i], BANK_ID));
if (head_ptr == $bits(head_ptr)'(j)) $write("*");
if (~ready_table[j]) $write("!");
$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
end
end
$write("\n");

3
hw/rtl/cache/VX_cache_req_queue.v vendored
View file

@ -83,7 +83,8 @@ module VX_cache_req_queue #(
.pop (pop_qual),
.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
.empty (o_empty),
.full (reqq_full)
.full (reqq_full),
`UNUSED_PIN(size)
);
wire[NUM_REQUESTS-1:0] real_out_per_valids = out_per_valids & {NUM_REQUESTS{~out_empty}};

3
hw/rtl/cache/VX_prefetcher.v vendored
View file

@ -46,7 +46,8 @@ module VX_prefetcher #(
.data_out(current_addr),
.empty (current_empty),
.full (current_full)
.full (current_full),
`UNUSED_PIN(size)
);
assign pref_valid = 0; // TODO use_valid != 0;