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minor update

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This commit is contained in:
Blaise Tine 2024-09-29 07:52:53 -07:00
parent 5c694a997c
commit cf3909a910
3 changed files with 15 additions and 16 deletions
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12
hw/rtl/libs/VX_encoder.sv
View file

@ -40,8 +40,8 @@ module VX_encoder #(
end else if (MODEL == 1) begin : g_model1
localparam M = 1 << LN;
`IGNORE_UNOPTFLAT_BEGIN
wire [LN-1:0][M-1:0] addr;
wire [LN:0][M-1:0] v;
wire [M-1:0] addr [LN];
wire [M-1:0] v [LN+1];
`IGNORE_UNOPTFLAT_END
// base case, also handle padding for non-power of two inputs
@ -50,19 +50,17 @@ module VX_encoder #(
for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin : g_scan_l
localparam SN = 1 << (LN - lvl);
localparam SI = M / SN;
localparam SW = lvl;
for (genvar s = 0; s < SN; ++s) begin : g_scan_s
`IGNORE_UNOPTFLAT_BEGIN
wire [1:0] vs = {v[lvl-1][s*SI+(SI>>1)], v[lvl-1][s*SI]};
`IGNORE_UNOPTFLAT_END
assign v[lvl][s*SI] = (| vs);
if (lvl == 1) begin : g_lvl_1
assign addr[lvl-1][s*SI +: SW] = vs[!REVERSE];
assign addr[lvl-1][s*SI +: lvl] = vs[!REVERSE];
end else begin : g_lvl_n
assign addr[lvl-1][s*SI +: SW] = {
assign addr[lvl-1][s*SI +: lvl] = {
vs[!REVERSE],
addr[lvl-2][s*SI +: SW-1] | addr[lvl-2][s*SI+(SI>>1) +: SW-1]
addr[lvl-2][s*SI +: lvl-1] | addr[lvl-2][s*SI+(SI>>1) +: lvl-1]
};
end
end

16
hw/rtl/libs/VX_find_first.sv
View file

@ -28,10 +28,10 @@ module VX_find_first #(
localparam TL = (1 << LOGN) - 1;
localparam TN = (1 << (LOGN+1)) - 1;
`IGNORE_WARNINGS_BEGIN
wire [TN-1:0] s_n;
wire [TN-1:0][DATAW-1:0] d_n;
`IGNORE_WARNINGS_END
`IGNORE_UNOPTFLAT_BEGIN
wire s_n [TN];
wire [DATAW-1:0] d_n [TN];
`IGNORE_UNOPTFLAT_END
for (genvar i = 0; i < N; ++i) begin : g_reverse
assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i];
@ -46,9 +46,11 @@ module VX_find_first #(
end
for (genvar j = 0; j < LOGN; ++j) begin : g_scan
for (genvar i = 0; i < (2**j); ++i) begin : g_i
assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1];
assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1];
localparam I = 1 << j;
for (genvar i = 0; i < I; ++i) begin : g_i
localparam K = I+i-1;
assign s_n[K] = s_n[2*K+1] | s_n[2*K+2];
assign d_n[K] = s_n[2*K+1] ? d_n[2*K+1] : d_n[2*K+2];
end
end

3
hw/rtl/libs/VX_pipe_buffer.sv
View file

@ -46,7 +46,7 @@ module VX_pipe_buffer #(
end else begin : g_register
wire [DEPTH:0] valid;
`IGNORE_UNOPTFLAT_BEGIN
wire [DEPTH:0] ready;
wire ready [DEPTH+1];
`IGNORE_UNOPTFLAT_END
wire [DEPTH:0][DATAW-1:0] data;
@ -71,7 +71,6 @@ module VX_pipe_buffer #(
assign valid_out = valid[DEPTH];
assign data_out = data[DEPTH];
assign ready[DEPTH] = ready_out;
end
endmodule