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This commit is contained in:
felsabbagh3 2019-03-27 13:52:13 -04:00
parent 68f3ba84e5
commit d02c3d25b7
27 changed files with 3105 additions and 1432 deletions
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53
rtl/VX_decode.v
View file

@ -101,29 +101,6 @@ module VX_decode(
// wire[31:0] internal_rd1;
// wire[31:0] internal_rd2;
// always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
genvar index;
generate
for (index=0; index < `NT; index=index+1)
begin: gen_code_label
VX_register_file vx_register_file(
.clk(clk),
.in_valid(in_wb_valid[index]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[index]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[index]),
.out_src2_data(rd2_register[index])
);
end
endgenerate
// VX_register_file vx_register_file_0(
// .clk(clk),
// .in_valid(in_wb_valid[0]),
@ -152,6 +129,36 @@ module VX_decode(
assign out_valid = in_valid;
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
always @(posedge clk) begin
$display("Decode: curr_pc: %h", in_curr_PC);
end
genvar index;
generate
for (index=0; index < `NT; index=index+1)
begin: gen_code_label
VX_register_file vx_register_file(
.clk(clk),
.in_valid(in_wb_valid[index]),
.in_write_register(write_register),
.in_rd(in_rd),
.in_data(in_write_data[index]),
.in_src1(out_rs1),
.in_src2(out_rs2),
.out_src1_data(rd1_register[index]),
.out_src2_data(rd2_register[index])
);
end
endgenerate
assign curr_opcode = in_instruction[6:0];

6
rtl/VX_define.h
View file

@ -1,8 +1,8 @@
#define NT 2
#define NT_M1 1
#define NT_T2_M1 3
#define NT 1
#define NT_M1 0
#define NT_T2_M1 1
#define R_INST 51
#define L_INST 3

6
rtl/VX_define.v
View file

@ -1,7 +1,7 @@
`define NT 2
`define NT_M1 1
`define NT_T2_M1 3
`define NT 1
`define NT_M1 0
`define NT_T2_M1 1
`define R_INST 7'd51

2
rtl/VX_fetch.v
View file

@ -52,7 +52,7 @@ module VX_fetch (
// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
// valid[ini_cur_th] = 1; // Thread 1 active
valid[0] = 1;
valid[1] = 0;
// valid[1] = 0;
stall_reg = 0;
delay_reg = 0;
old = 0;

2
rtl/VX_register_file.v
View file

@ -35,7 +35,7 @@ module VX_register_file (
always @(posedge clk) begin
if(write_enable) begin
// $display("Writing %h to %d",write_data, write_register);
$display("Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end
end

11
rtl/VX_writeback.v
View file

@ -3,6 +3,7 @@
module VX_writeback (
input wire clk,
input wire[31:0] in_alu_result[`NT_M1:0],
input wire[31:0] in_mem_result[`NT_M1:0],
input wire[4:0] in_rd,
@ -17,12 +18,12 @@ module VX_writeback (
wire is_jal;
wire uses_alu;
// always @(*) begin
// if (in_PC_next == 32'h800001f4 || in_PC_next == 32'h800001f0) begin
always @(negedge clk) begin
if (in_wb != 0) begin
// $display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result, in_rd);
// end
// end
$display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result[0], in_rd);
end
end
wire[31:0] out_pc_data[`NT_M1:0];

3
rtl/Vortex.v
View file

@ -381,7 +381,7 @@ VX_e_m_reg vx_e_m_reg(
wire[31:0] use_rd2[`NT_M1:0];
assign use_rd2[0] = e_m_reg_data[1];
assign use_rd2[1] = e_m_reg_data[3];
// assign use_rd2[1] = e_m_reg_data[3];
VX_memory vx_memory(
.in_alu_result (e_m_alu_result),
@ -441,6 +441,7 @@ VX_m_w_reg vx_m_w_reg(
VX_writeback vx_writeback(
.clk (clk),
.in_alu_result (m_w_alu_result),
.in_mem_result (m_w_mem_result),
.in_rd (m_w_rd),

BIN
rtl/obj_dir/VVortex
View file

Binary file not shown.

1376
rtl/obj_dir/VVortex.cpp
View file

File diff suppressed because it is too large Load diff

205
rtl/obj_dir/VVortex.h
View file

@ -8,7 +8,7 @@
#ifndef _VVortex_H_
#define _VVortex_H_
#include "verilated.h"
#include "verilated_heavy.h"
class VVortex__Syms;
@ -27,10 +27,10 @@ VL_MODULE(VVortex) {
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0);
VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[2],31,0);
VL_OUT(out_cache_driver_in_address[2],31,0);
VL_OUT8(out_cache_driver_in_valid[2],0,0);
VL_OUT(out_cache_driver_in_data[2],31,0);
VL_IN(in_cache_driver_out_data[1],31,0);
VL_OUT(out_cache_driver_in_address[1],31,0);
VL_OUT8(out_cache_driver_in_valid[1],0,0);
VL_OUT(out_cache_driver_in_data[1],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
@ -41,14 +41,12 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
@ -101,60 +99,57 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
VL_SIG(Vortex__DOT__decode_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__execute_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__use_rd2[2],31,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
VL_SIG8(Vortex__DOT__fetch_valid[1],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[1],0,0);
VL_SIG(Vortex__DOT__decode_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__decode_valid[1],0,0);
VL_SIG(Vortex__DOT__d_e_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[1],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[1],31,0);
VL_SIG(Vortex__DOT__execute_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__execute_valid[1],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[1],31,0);
VL_SIG(Vortex__DOT__e_m_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[1],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[1],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[1],31,0);
VL_SIG8(Vortex__DOT__memory_valid[1],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[1],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[1],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[1],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[1],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[1],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[1],31,0);
VL_SIG(Vortex__DOT__use_rd2[1],31,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[1],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[1],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[1],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[1],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[1],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[1],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[1],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@ -166,63 +161,59 @@ VL_MODULE(VVortex) {
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[1],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__0__KET____DOT__vx_alu__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_alu__in_reg_data[2],31,0);
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES

2
rtl/obj_dir/VVortex.mk
View file

@ -10,7 +10,7 @@ default: VVortex
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)

BIN
rtl/obj_dir/VVortex__ALL.a
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6
rtl/obj_dir/VVortex__ALLcls.d
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@ -1,4 +1,4 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex__Syms.h
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h

BIN
rtl/obj_dir/VVortex__ALLcls.o
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6
rtl/obj_dir/VVortex__ALLsup.d
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@ -1,4 +1,4 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
VVortex.h
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex.h

BIN
rtl/obj_dir/VVortex__ALLsup.o
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2
rtl/obj_dir/VVortex__Syms.h
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@ -6,7 +6,7 @@
#ifndef _VVortex__Syms_H_
#define _VVortex__Syms_H_
#include "verilated.h"
#include "verilated_heavy.h"
// INCLUDE MODULE CLASSES
#include "VVortex.h"

2
rtl/obj_dir/VVortex__ver.d
View file

@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v

48
rtl/obj_dir/VVortex__verFiles.dat
View file

@ -1,26 +1,26 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2782 12889318286 1553669148 0 1553669148 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v"
S 10713 12889318288 1553673019 0 1553673019 0 "VX_decode.v"
S 1551 12889079483 1553661565 0 1553661565 0 "VX_define.v"
S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v"
S 3370 12889318290 1553673095 0 1553673095 0 "VX_execute.v"
S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 3941 12889047675 1553673132 0 1553673132 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 2790 12889084513 1553673201 0 1553673201 0 "VX_memory.v"
S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v"
S 1010 12889086287 1553671609 0 1553671609 0 "VX_writeback.v"
S 15611 12889318291 1553672889 0 1553672889 0 "Vortex.v"
T 190167 12889376837 1553673213 0 1553673213 0 "obj_dir/VVortex.cpp"
T 14844 12889376836 1553673213 0 1553673213 0 "obj_dir/VVortex.h"
T 1800 12889376839 1553673213 0 1553673213 0 "obj_dir/VVortex.mk"
T 530 12889376835 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.cpp"
T 711 12889376834 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.h"
T 464 12889376840 1553673213 0 1553673213 0 "obj_dir/VVortex__ver.d"
T 0 0 1553673213 0 1553673213 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889376838 1553673213 0 1553673213 0 "obj_dir/VVortex_classes.mk"
S 5163137 401094 1553636247 412576209 1553636247 412576209 "/usr/local/bin/verilator_bin"
S 2782 5518365 1553641993 611294425 1553641993 611294425 "VX_alu.v"
S 1495 5518326 1553635490 361093288 1553635490 361093288 "VX_csr_handler.v"
S 4780 5518327 1553705050 153020819 1553705050 153020819 "VX_d_e_reg.v"
S 10711 5518328 1553706261 998510628 1553706261 998510628 "VX_decode.v"
S 1551 5518330 1553706438 435305366 1553706438 435305366 "VX_define.v"
S 3941 5518331 1553705050 153020819 1553705050 153020819 "VX_e_m_reg.v"
S 3370 5518332 1553705050 153020819 1553705050 153020819 "VX_execute.v"
S 1382 5518333 1553705050 153020819 1553705050 153020819 "VX_f_d_reg.v"
S 3944 5518334 1553706489 155533656 1553706489 155533656 "VX_fetch.v"
S 5632 5518335 1553705050 153020819 1553705050 153020819 "VX_forwarding.v"
S 1677 5518336 1553705050 153020819 1553705050 153020819 "VX_m_w_reg.v"
S 2790 5518337 1553705050 153020819 1553705050 153020819 "VX_memory.v"
S 997 5518338 1553705589 591472686 1553705589 591472686 "VX_register_file.v"
S 986 5518339 1553706081 977698760 1553706081 977698760 "VX_writeback.v"
S 15638 5518364 1553706457 931393127 1553706457 931393127 "Vortex.v"
T 134893 5518343 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex.cpp"
T 13928 5518342 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex.h"
T 1777 5518345 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex.mk"
T 530 5518341 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex__Syms.cpp"
T 717 5518340 1553706491 723545213 1553706491 723545213 "obj_dir/VVortex__Syms.h"
T 418 5518346 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex__ver.d"
T 0 0 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex__verFiles.dat"
T 1159 5518344 1553706491 727545232 1553706491 727545232 "obj_dir/VVortex_classes.mk"

2598
rtl/obj_dir/debug.txt Normal file
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File diff suppressed because it is too large Load diff

7
rtl/obj_dir/test_bench.d
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@ -1,4 +1,5 @@
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
VVortex.h /usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h

BIN
rtl/obj_dir/test_bench.o
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17
rtl/obj_dir/verilated.d
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@ -1,9 +1,8 @@
verilated.o: \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

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rtl/obj_dir/verilated.o
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9
rtl/results.txt
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@ -0,0 +1,9 @@
**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex ****************
# Dynamic Instructions: 496
# of total cycles: 500
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00806
# time to simulate: 2.13149e-317 milliseconds
# GRADE: Failed on test: 4294967295

128
rtl/test_bench.cpp
View file

@ -12,77 +12,77 @@ int main(int argc, char **argv)
Vortex v;
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../emulator/riscv_tests/rv32ui-p-add.hex",
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
"../../emulator/riscv_tests/rv32ui-p-and.hex",
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
"../../emulator/riscv_tests/rv32ui-p-or.hex",
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
"../../emulator/riscv_tests/rv32um-p-div.hex",
"../../emulator/riscv_tests/rv32um-p-divu.hex",
"../../emulator/riscv_tests/rv32um-p-mul.hex",
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
"../../emulator/riscv_tests/rv32um-p-rem.hex",
"../../emulator/riscv_tests/rv32um-p-remu.hex"
};
// bool passed = true;
// std::string tests[NUM_TESTS] = {
// "../../emulator/riscv_tests/rv32ui-p-add.hex",
// "../../emulator/riscv_tests/rv32ui-p-addi.hex",
// "../../emulator/riscv_tests/rv32ui-p-and.hex",
// "../../emulator/riscv_tests/rv32ui-p-andi.hex",
// "../../emulator/riscv_tests/rv32ui-p-auipc.hex",
// "../../emulator/riscv_tests/rv32ui-p-beq.hex",
// "../../emulator/riscv_tests/rv32ui-p-bge.hex",
// "../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
// "../../emulator/riscv_tests/rv32ui-p-blt.hex",
// "../../emulator/riscv_tests/rv32ui-p-bltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-bne.hex",
// "../../emulator/riscv_tests/rv32ui-p-jal.hex",
// "../../emulator/riscv_tests/rv32ui-p-jalr.hex",
// "../../emulator/riscv_tests/rv32ui-p-lb.hex",
// "../../emulator/riscv_tests/rv32ui-p-lbu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lh.hex",
// "../../emulator/riscv_tests/rv32ui-p-lhu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lui.hex",
// "../../emulator/riscv_tests/rv32ui-p-lw.hex",
// "../../emulator/riscv_tests/rv32ui-p-or.hex",
// "../../emulator/riscv_tests/rv32ui-p-ori.hex",
// "../../emulator/riscv_tests/rv32ui-p-sb.hex",
// "../../emulator/riscv_tests/rv32ui-p-sh.hex",
// "../../emulator/riscv_tests/rv32ui-p-simple.hex",
// "../../emulator/riscv_tests/rv32ui-p-sll.hex",
// "../../emulator/riscv_tests/rv32ui-p-slli.hex",
// "../../emulator/riscv_tests/rv32ui-p-slt.hex",
// "../../emulator/riscv_tests/rv32ui-p-slti.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sra.hex",
// "../../emulator/riscv_tests/rv32ui-p-srai.hex",
// "../../emulator/riscv_tests/rv32ui-p-srl.hex",
// "../../emulator/riscv_tests/rv32ui-p-srli.hex",
// "../../emulator/riscv_tests/rv32ui-p-sub.hex",
// "../../emulator/riscv_tests/rv32ui-p-sw.hex",
// "../../emulator/riscv_tests/rv32ui-p-xor.hex",
// "../../emulator/riscv_tests/rv32ui-p-xori.hex",
// "../../emulator/riscv_tests/rv32um-p-div.hex",
// "../../emulator/riscv_tests/rv32um-p-divu.hex",
// "../../emulator/riscv_tests/rv32um-p-mul.hex",
// "../../emulator/riscv_tests/rv32um-p-mulh.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhu.hex",
// "../../emulator/riscv_tests/rv32um-p-rem.hex",
// "../../emulator/riscv_tests/rv32um-p-remu.hex"
// };
for (int ii = 0; ii < NUM_TESTS; ii++)
// for (int ii = 0; ii < NUM_TESTS - 1; ii++)
{
bool curr = v.simulate(tests[ii]);
// for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 0; ii < NUM_TESTS - 1; ii++)
// {
// bool curr = v.simulate(tests[ii]);
if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
passed = passed && curr;
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
// passed = passed && curr;
std::cerr << DEFAULT;
}
// std::cerr << DEFAULT;
// }
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
// if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// char testing[] = "../../src/riscv_tests/rv32ui-p-lw.hex";
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sub.hex";
// bool curr = v.simulate(testing);
// if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return 0;

48
rtl/test_bench.h
View file

@ -142,6 +142,8 @@ bool Vortex::ibus_driver()
ram.getWord(new_PC, &curr_inst);
vortex->fe_instruction = curr_inst;
printf("\n\n(%x) Inst: %x\n", new_PC, curr_inst);
////////////////////// IBUS //////////////////////
@ -284,20 +286,49 @@ bool Vortex::simulate(std::string file_to_simulate)
unsigned new_PC;
int cycle = 0;
while (this->stop && (!(stop && (counter > 5))))
{
// while (this->stop && (!(stop && (counter > 5))))
// {
// std::cout << "************* Cycle: " << cycle << "\n";
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
for (int i = 0; i < 500; i++)
{
// std::cout << "************* Cycle: " << cycle << "\n";
bool istop = ibus_driver();
bool dstop = !dbus_driver();
vortex->clk = 1;
vortex->eval();
vortex->clk = 1;
vortex->eval();
vortex->clk = 0;
vortex->eval();
vortex->clk = 0;
vortex->eval();
stop = istop && dstop;
@ -311,7 +342,8 @@ bool Vortex::simulate(std::string file_to_simulate)
}
cycle++;
}
}
uint32_t status;
ram.getWord(0, &status);