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minor update

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This commit is contained in:
Blaise Tine 2022-03-06 18:23:13 -05:00
parent eca418a198
commit d241fc9a4b
6 changed files with 21 additions and 23 deletions
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12
hw/rtl/VX_types.vh
View file

@ -278,11 +278,10 @@
`define ROP_STATE_STENCIL_MASK 11
`define ROP_STATE_STENCIL_REF 12
`define ROP_STATE_BLEND_MODE 13
`define ROP_STATE_BLEND_SRC 14
`define ROP_STATE_BLEND_DST 15
`define ROP_STATE_BLEND_CONST 16
`define ROP_STATE_LOGIC_OP 17
`define ROP_STATE_COUNT 18
`define ROP_STATE_BLEND_FUNC 14
`define ROP_STATE_BLEND_CONST 15
`define ROP_STATE_LOGIC_OP 16
`define ROP_STATE_COUNT 17
`define DCR_ROP_STATE_BEGIN `DCR_RASTER_STATE_END
`define DCR_ROP_CBUF_ADDR (`DCR_ROP_STATE_BEGIN+`ROP_STATE_CBUF_ADDR)
@ -299,8 +298,7 @@
`define DCR_ROP_STENCIL_MASK (`DCR_ROP_STATE_BEGIN+`ROP_STATE_STENCIL_MASK)
`define DCR_ROP_STENCIL_REF (`DCR_ROP_STATE_BEGIN+`ROP_STATE_STENCIL_REF)
`define DCR_ROP_BLEND_MODE (`DCR_ROP_STATE_BEGIN+`ROP_STATE_BLEND_MODE)
`define DCR_ROP_BLEND_SRC (`DCR_ROP_STATE_BEGIN+`ROP_STATE_BLEND_SRC)
`define DCR_ROP_BLEND_DST (`DCR_ROP_STATE_BEGIN+`ROP_STATE_BLEND_DST)
`define DCR_ROP_BLEND_FUNC (`DCR_ROP_STATE_BEGIN+`ROP_STATE_BLEND_FUNC)
`define DCR_ROP_BLEND_CONST (`DCR_ROP_STATE_BEGIN+`ROP_STATE_BLEND_CONST)
`define DCR_ROP_LOGIC_OP (`DCR_ROP_STATE_BEGIN+`ROP_STATE_LOGIC_OP)
`define DCR_ROP_STATE_END (`DCR_ROP_STATE_BEGIN+`ROP_STATE_COUNT)

12
hw/rtl/rop_unit/VX_rop_dcr.sv
View file

@ -71,13 +71,11 @@ module VX_rop_dcr (
dcrs.blend_mode_rgb <= dcr_wr_data[15:0][`ROP_BLEND_MODE_BITS-1:0];
dcrs.blend_mode_a <= dcr_wr_data[31:16][`ROP_BLEND_MODE_BITS-1:0];
end
`DCR_ROP_BLEND_SRC: begin
dcrs.blend_src_rgb <= dcr_wr_data[15:0][`ROP_BLEND_FUNC_BITS-1:0];
dcrs.blend_src_a <= dcr_wr_data[31:16][`ROP_BLEND_FUNC_BITS-1:0];
end
`DCR_ROP_BLEND_DST: begin
dcrs.blend_dst_rgb <= dcr_wr_data[15:0][`ROP_BLEND_FUNC_BITS-1:0];
dcrs.blend_dst_a <= dcr_wr_data[31:16][`ROP_BLEND_FUNC_BITS-1:0];
`DCR_ROP_BLEND_FUNC: begin
dcrs.blend_src_rgb <= dcr_wr_data[0 +: 8][`ROP_BLEND_FUNC_BITS-1:0];
dcrs.blend_src_a <= dcr_wr_data[8 +: 8][`ROP_BLEND_FUNC_BITS-1:0];
dcrs.blend_dst_rgb <= dcr_wr_data[16 +: 8][`ROP_BLEND_FUNC_BITS-1:0];
dcrs.blend_dst_a <= dcr_wr_data[24 +: 8][`ROP_BLEND_FUNC_BITS-1:0];
end
`DCR_ROP_BLEND_CONST: begin
dcrs.blend_const <= dcr_wr_data[31:0];

3
hw/rtl/rop_unit/VX_rop_define.vh
View file

@ -21,8 +21,7 @@ task trace_rop_state (
`DCR_ROP_STENCIL_MASK: dpi_trace("STENCIL_MASK");
`DCR_ROP_STENCIL_REF: dpi_trace("STENCIL_REF");
`DCR_ROP_BLEND_MODE: dpi_trace("BLEND_MODE");
`DCR_ROP_BLEND_SRC: dpi_trace("BLEND_SRC");
`DCR_ROP_BLEND_DST: dpi_trace("BLEND_DST");
`DCR_ROP_BLEND_FUNC: dpi_trace("BLEND_FUNC");
`DCR_ROP_BLEND_CONST: dpi_trace("BLEND_CONST");
`DCR_ROP_LOGIC_OP: dpi_trace("LOGIC_OP");
default: dpi_trace("??");

8
sim/simx/ropunit.cpp
View file

@ -398,10 +398,10 @@ private:
write_mask_ = dcrs_.at(DCR_ROP_CBUF_MASK);
blend_mode_rgb_ = dcrs_.at(DCR_ROP_BLEND_MODE) & 0xffff;
blend_mode_a_ = dcrs_.at(DCR_ROP_BLEND_MODE) >> 16;
blend_src_rgb_ = dcrs_.at(DCR_ROP_BLEND_SRC) & 0xffff;
blend_src_a_ = dcrs_.at(DCR_ROP_BLEND_SRC) >> 16;
blend_dst_rgb_ = dcrs_.at(DCR_ROP_BLEND_DST) & 0xffff;
blend_dst_a_ = dcrs_.at(DCR_ROP_BLEND_DST) >> 16;
blend_src_rgb_ = (dcrs_.at(DCR_ROP_BLEND_FUNC) >> 0) & 0xff;
blend_src_a_ = (dcrs_.at(DCR_ROP_BLEND_FUNC) >> 8) & 0xff;
blend_dst_rgb_ = (dcrs_.at(DCR_ROP_BLEND_FUNC) >> 16) & 0xff;
blend_dst_a_ = (dcrs_.at(DCR_ROP_BLEND_FUNC) >> 24) & 0xff;
blend_const_ = dcrs_.at(DCR_ROP_BLEND_CONST);
logic_op_ = dcrs_.at(DCR_ROP_LOGIC_OP);
initialized_ = true;

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9
tests/regression/draw3d/main.cpp
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@ -330,9 +330,12 @@ int main(int argc, char *argv[]) {
vx_dcr_write(device, DCR_ROP_STENCIL_REF, 0);
// configure rop blend stats
vx_dcr_write(device, DCR_ROP_BLEND_MODE, (ROP_BLEND_MODE_ADD << 16) | ROP_BLEND_MODE_ADD);
vx_dcr_write(device, DCR_ROP_BLEND_SRC, (ROP_BLEND_FUNC_ONE << 16) | ROP_BLEND_FUNC_SRC_A);
vx_dcr_write(device, DCR_ROP_BLEND_DST, (ROP_BLEND_FUNC_ZERO << 16) | ROP_BLEND_FUNC_ONE_MINUS_SRC_A);
vx_dcr_write(device, DCR_ROP_BLEND_MODE, (ROP_BLEND_MODE_ADD << 16) // DST
| (ROP_BLEND_MODE_ADD << 0)); // SRC
vx_dcr_write(device, DCR_ROP_BLEND_FUNC, (ROP_BLEND_FUNC_ZERO << 24) // DST_A
| (ROP_BLEND_FUNC_ONE_MINUS_SRC_A << 16) // DST_RGB
| (ROP_BLEND_FUNC_ONE << 8) // SRC_A
| (ROP_BLEND_FUNC_SRC_A << 0)); // SRC_RGB
vx_dcr_write(device, DCR_ROP_LOGIC_OP, ROP_LOGIC_OP_COPY);
// run tests