Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev

hw/rtl/cache/VX_bank.v

@@ -94,7 +94,10 @@ module VX_bank #(
     // Snoop Response
     output wire                         snp_rsp_valid,
     output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
-    input  wire                         snp_rsp_ready
+    input  wire                         snp_rsp_ready,
+
+    // Misses
+    output wire misses
 );
 
 `ifdef DBG_CORE_REQ_INFO
@@ -441,6 +444,8 @@ module VX_bank #(
         .dirty_out      (dirty_st1),
         .writeen_out    (writeen_st1)
     );
+
+    assign misses = miss_st1;
     
     wire                            valid_st2;    
     wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;

hw/rtl/cache/VX_cache.v

@@ -119,7 +119,9 @@ module VX_cache #(
     input wire [NUM_SNP_REQUESTS-1:0]       snp_fwdin_valid,    
     input wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
 `IGNORE_WARNINGS_END
-    output wire [NUM_SNP_REQUESTS-1:0]      snp_fwdin_ready
+    output wire [NUM_SNP_REQUESTS-1:0]      snp_fwdin_ready,
+
+    output wire [NUM_BANKS-1:0] miss_vec
 );
 
     wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0]      per_bank_valid;
@@ -147,6 +149,11 @@ module VX_cache #(
     wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
     wire [NUM_BANKS-1:0]                        per_bank_snp_rsp_ready;
 
+    wire [NUM_BANKS-1:0]                        per_bank_miss; 
+    assign miss_vec = per_bank_miss; 
+
+   
+
     wire                         snp_req_valid_qual;    
     wire [`DRAM_ADDR_WIDTH-1:0]  snp_req_addr_qual;
     wire                         snp_req_invalidate_qual;    
@@ -260,6 +267,9 @@ module VX_cache #(
         wire [SNP_REQ_TAG_WIDTH-1:0]    curr_bank_snp_rsp_tag;
         wire                            curr_bank_snp_rsp_ready;                    
 
+        wire                            curr_bank_core_req_ready;
+        wire                            curr_bank_miss; 
+
         // Core Req
         assign curr_bank_core_req_valid   = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}});
         assign curr_bank_core_req_addr    = core_req_addr;
@@ -315,6 +325,9 @@ module VX_cache #(
         assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid;
         assign per_bank_snp_rsp_tag[i]   = curr_bank_snp_rsp_tag;
         assign curr_bank_snp_rsp_ready   = per_bank_snp_rsp_ready[i];
+
+        //Misses
+        assign per_bank_miss[i] = curr_bank_miss; 
         
         VX_bank #(                
             .BANK_ID            (i),
@@ -380,9 +393,12 @@ module VX_cache #(
             .snp_req_ready      (curr_bank_snp_req_ready),
 
             // Snoop response
-            .snp_rsp_valid      (curr_bank_snp_rsp_valid),
-            .snp_rsp_tag        (curr_bank_snp_rsp_tag),
-            .snp_rsp_ready      (curr_bank_snp_rsp_ready)
+            .snp_rsp_valid           (curr_bank_snp_rsp_valid),
+            .snp_rsp_tag             (curr_bank_snp_rsp_tag),
+            .snp_rsp_ready           (curr_bank_snp_rsp_ready),
+
+            //Misses
+            .misses                  (curr_bank_miss)
         );
     end   
 

hw/unit_tests/cache/cachesim.cpp

@@ -4,6 +4,7 @@
 #include <iostream>
 #include <vector>
 #include <map>
+#include <bitset> 
 
 uint64_t timestamp = 0;
 
@@ -88,14 +89,26 @@ void CacheSim::run(){
   this->step();
 
   int valid = 300; 
+  int stalls = 20 + 10; 
   
   while (valid > -1) {
 
       this->step();
+      display_miss(); 
+      if(cache_->core_rsp_valid){
+        get_core_rsp();
+      }
+      
       if(!cache_->core_req_valid && !cache_->core_rsp_valid){
         valid--; 
+       
+      }
+      stalls--; 
+      if (stalls == 20){
+          //stall_dram(); 
+          //send_snoop_req(); 
+          stalls--; 
       }
-      this->display_hit_miss();
   }
 }
 
@@ -156,6 +169,17 @@ void CacheSim::eval_rsps(){
   }
 }
 
+void CacheSim::stall_dram(){
+  cache_->dram_req_ready = 0;
+}
+
+void CacheSim::send_snoop_req(){
+    cache_->snp_req_valid = 1;
+    cache_->snp_req_addr = 0x12222222;
+    cache_->snp_req_invalidate = 1; 
+    cache_->snp_req_tag = 0xff; 
+}
+
 void CacheSim::eval_dram_bus() {
   if (ram_ == nullptr) {
     cache_->dram_req_ready = 0;
@@ -250,7 +274,14 @@ bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){
 
 //DEBUG
 
-void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
+void CacheSim::display_miss(){
+  int i = (unsigned int)cache_->miss_vec; 
+  std::bitset<8> x(i); 
+  if (i) std::cout << "Miss Vec " << x << std::endl;
+  //std::cout << "Miss Vec 0" << cache_->miss_vec[0] << std::endl;
+}
+
+void CacheSim::get_core_req(unsigned int (&rsp)[4]){
   rsp[0] = cache_->core_rsp_data[0];
   rsp[1] = cache_->core_rsp_data[1];
   rsp[2] = cache_->core_rsp_data[2];
@@ -261,15 +292,15 @@ void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
   //std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
 }
 
-void CacheSim::get_core_req(){
+void CacheSim::get_core_rsp(){
   //std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl; 
-  char check = cache_->core_req_valid;
-  std::cout << std::hex << "core_req_valid: " << check << std::endl;
-  std::cout << std::hex << "core_req_data[0]: " << cache_->core_req_data[0] << std::endl;
-  std::cout << std::hex << "core_req_data[1]: " << cache_->core_req_data[1] << std::endl;
-  std::cout << std::hex << "core_req_data[2]: " << cache_->core_req_data[2] << std::endl;
-  std::cout << std::hex << "core_req_data[3]: " << cache_->core_req_data[3] << std::endl;
-  std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl; 
+  char check = cache_->core_rsp_valid;
+  std::cout << std::hex << "core_rsp_valid: " << (unsigned int) check << std::endl;
+  std::cout << std::hex << "core_rsp_data[0]: " << cache_->core_rsp_data[0] << std::endl;
+  std::cout << std::hex << "core_rsp_data[1]: " << cache_->core_rsp_data[1] << std::endl;
+  std::cout << std::hex << "core_rsp_data[2]: " << cache_->core_rsp_data[2] << std::endl;
+  std::cout << std::hex << "core_rsp_data[3]: " << cache_->core_rsp_data[3] << std::endl;
+  std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; 
 }
 
 void CacheSim::get_dram_req(){
@@ -288,7 +319,3 @@ void CacheSim::get_dram_rsp(){
   std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl;
 }
 
-void CacheSim::display_hit_miss(){
-  std::cout << std::hex << "Misses: " << cache_->misses << std::endl; 
-}
-

hw/unit_tests/cache/cachesim.h

@@ -47,28 +47,30 @@ public:
   void step();
   void wait(uint32_t cycles); 
   void attach_ram(RAM* ram);
-
   void run();  //run until all reqs are empty
-  void clear_req(); 
+ 
+  //req/rsp
   void send_req(core_req_t *req);
+  void clear_req(); 
+  void stall_dram();
+  void send_snoop_req();
+  void send_snp_fwd_in(); 
+
+  //assert funcs
   bool assert_equal(unsigned int* data, unsigned int tag);
-  //void time_analyisis 
-
-  //display funcs
 
+  //debug funcs
   void get_dram_req();
-  void get_core_rsp(unsigned int (&rsp)[4]);
-  void get_core_req();
+  void get_core_req(unsigned int (&rsp)[4]);
+  void get_core_rsp();
   bool get_core_req_ready();
   bool get_core_rsp_ready();
   void get_dram_rsp();
-  void display_hit_miss(); 
-
+  void display_miss();
 
 private:  
 
   void eval();  
-
   void eval_reqs(); 
   void eval_rsps();
   void eval_dram_bus();

hw/unit_tests/cache/testbench.cpp

@@ -38,9 +38,9 @@ int REQ_RSP(CacheSim *sim){ //verified
 
   sim->run();
 
-  bool check = sim->assert_equal(data, write->tag);
+  int check = sim->assert_equal(data, write->tag);
   
-  return check;
+  if (check == 4) return 1; 
 }
 
 int HIT_1(CacheSim *sim){
@@ -82,8 +82,8 @@ int HIT_1(CacheSim *sim){
 
 int MISS_1(CacheSim *sim){
   unsigned int addr1[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
-  unsigned int addr2[4] = {0x12244444, 0xabb0bbbb, 0xcddd0ddd, 0xe0444444};
-  unsigned int addr3[4] = {0x12888888, 0xa0bbbbbb, 0xcddddd0d, 0xe4444440};
+  unsigned int addr2[4] = {0x12229222, 0xabbbb4bb, 0xcddd47dd, 0xe4423544};
+  unsigned int addr3[4] = {0x12223332, 0xabb454bb, 0xcdddeefd, 0xe4447744};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};
   char responded = 0;
@@ -105,7 +105,6 @@ int MISS_1(CacheSim *sim){
   read1->data = data; 
   read1->tag = 0xff;
 
-  //read req
   core_req_t* read2 = new core_req_t;
   read2->valid = 0xf;
   read2->rw = 0;
@@ -113,8 +112,7 @@ int MISS_1(CacheSim *sim){
   read2->addr = addr2;
   read2->data = data; 
   read2->tag = 0xff;
-
-  //read req
+  
   core_req_t* read3 = new core_req_t;
   read3->valid = 0xf;
   read3->rw = 0;
@@ -127,12 +125,11 @@ int MISS_1(CacheSim *sim){
   sim->reset();
 
   //queue reqs
-  //sim->send_req(write);
+  sim->send_req(write);
   sim->send_req(read1);
   sim->send_req(read2);
   sim->send_req(read3);
 
-
   sim->run();
 
   bool check = sim->assert_equal(data, write->tag);
@@ -178,6 +175,7 @@ int FLUSH(CacheSim *sim){
 
 
 int BACK_PRESSURE(CacheSim *sim){
+  //happens whenever the core is stalled or DRAM is stalled
   unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
   unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
   unsigned int rsp[4] = {0,0,0,0};