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memory system interfaces refactoring

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This commit is contained in:
Blaise Tine 2023-06-22 15:42:20 -04:00
parent e4fec33f5d
commit d5e73b3478
41 changed files with 274 additions and 273 deletions
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2
hw/.gitignore vendored Normal file
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@ -0,0 +1,2 @@
VX_config.h
VX_types.h

1
hw/rtl/.gitignore vendored
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@ -1 +0,0 @@
/VX_user_config.vh

20
hw/rtl/VX_cluster.sv
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@ -27,8 +27,8 @@ module VX_cluster #(
input wire reset,
`ifdef PERF_ENABLE
VX_perf_memsys_if.master perf_memsys_if,
VX_perf_memsys_if.slave perf_memsys_total_if,
VX_mem_perf_if.master mem_perf_if,
VX_mem_perf_if.slave perf_memsys_total_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
@ -36,27 +36,27 @@ module VX_cluster #(
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_tex_perf_if.master perf_tex_if,
VX_perf_cache_if.master perf_tcache_if,
VX_cache_perf_if.master perf_tcache_if,
VX_tex_perf_if.slave perf_tex_total_if,
VX_perf_cache_if.slave perf_tcache_total_if,
VX_cache_perf_if.slave perf_tcache_total_if,
`endif
`endif
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_raster_perf_if.master perf_raster_if,
VX_perf_cache_if.master perf_rcache_if,
VX_cache_perf_if.master perf_rcache_if,
VX_raster_perf_if.slave perf_raster_total_if,
VX_perf_cache_if.slave perf_rcache_total_if,
VX_cache_perf_if.slave perf_rcache_total_if,
`endif
`endif
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_rop_perf_if.master perf_rop_if,
VX_perf_cache_if.master perf_ocache_if,
VX_cache_perf_if.master perf_ocache_if,
VX_rop_perf_if.slave perf_rop_total_if,
VX_perf_cache_if.slave perf_ocache_total_if,
VX_cache_perf_if.slave perf_ocache_total_if,
`endif
`endif
@ -371,7 +371,7 @@ module VX_cluster #(
.reset (mem_unit_reset),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.mem_perf_if (mem_perf_if),
`endif
.dcache_bus_if (per_socket_dcache_bus_if),
@ -434,7 +434,7 @@ module VX_cluster #(
.reset (socket_reset),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_total_if),
.mem_perf_if (perf_memsys_total_if),
`endif
.dcr_write_if (socket_dcr_write_if),

10
hw/rtl/VX_socket.sv
View file

@ -15,7 +15,7 @@ module VX_socket #(
input wire reset,
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_mem_perf_if.slave mem_perf_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
@ -31,7 +31,7 @@ module VX_socket #(
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
VX_cache_perf_if.slave perf_tcache_if,
`endif
VX_tex_bus_if.master tex_bus_if,
`endif
@ -39,7 +39,7 @@ module VX_socket #(
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_cache_perf_if.slave perf_rcache_if,
`endif
VX_raster_bus_if.slave raster_bus_if,
`endif
@ -47,7 +47,7 @@ module VX_socket #(
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_cache_perf_if.slave perf_ocache_if,
`endif
VX_rop_bus_if.master rop_bus_if,
`endif
@ -289,7 +289,7 @@ module VX_socket #(
.reset (core_reset),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.mem_perf_if (mem_perf_if),
`endif
.dcr_write_if (core_dcr_write_if),

56
hw/rtl/Vortex.sv
View file

@ -49,9 +49,9 @@ module Vortex (
);
`ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if[`NUM_CLUSTERS]();
VX_perf_memsys_if perf_memsys_total_if();
VX_perf_cache_if perf_l3cache_if();
VX_mem_perf_if mem_perf_if[`NUM_CLUSTERS]();
VX_mem_perf_if perf_memsys_total_if();
VX_cache_perf_if perf_l3cache_if();
`endif
VX_mem_bus_if #(
@ -80,9 +80,9 @@ module Vortex (
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_tex_perf_if perf_tex_if[`NUM_CLUSTERS]();
VX_perf_cache_if perf_tcache_if[`NUM_CLUSTERS]();
VX_cache_perf_if perf_tcache_if[`NUM_CLUSTERS]();
VX_tex_perf_if perf_tex_total_if();
VX_perf_cache_if perf_tcache_total_if();
VX_cache_perf_if perf_tcache_total_if();
`PERF_TEX_ADD (perf_tex_total_if, perf_tex_if, `NUM_CLUSTERS);
`PERF_CACHE_ADD (perf_tcache_total_if, perf_tcache_if, `NUM_CLUSTERS);
`endif
@ -91,9 +91,9 @@ module Vortex (
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_raster_perf_if perf_raster_if[`NUM_CLUSTERS]();
VX_perf_cache_if perf_rcache_if[`NUM_CLUSTERS]();
VX_cache_perf_if perf_rcache_if[`NUM_CLUSTERS]();
VX_raster_perf_if perf_raster_total_if();
VX_perf_cache_if perf_rcache_total_if();
VX_cache_perf_if perf_rcache_total_if();
`PERF_RASTER_ADD (perf_raster_total_if, perf_raster_if, `NUM_CLUSTERS);
`PERF_CACHE_ADD (perf_rcache_total_if, perf_rcache_if, `NUM_CLUSTERS);
`endif
@ -102,9 +102,9 @@ module Vortex (
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_rop_perf_if perf_rop_if[`NUM_CLUSTERS]();
VX_perf_cache_if perf_ocache_if[`NUM_CLUSTERS]();
VX_cache_perf_if perf_ocache_if[`NUM_CLUSTERS]();
VX_rop_perf_if perf_rop_total_if();
VX_perf_cache_if perf_ocache_total_if();
VX_cache_perf_if perf_ocache_total_if();
`PERF_ROP_ADD (perf_rop_total_if, perf_rop_if, `NUM_CLUSTERS);
`PERF_CACHE_ADD (perf_ocache_total_if, perf_ocache_if, `NUM_CLUSTERS);
`endif
@ -149,7 +149,7 @@ module Vortex (
.reset (cluster_reset),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if[i]),
.mem_perf_if (mem_perf_if[i]),
.perf_memsys_total_if (perf_memsys_total_if),
`endif
@ -221,7 +221,7 @@ module Vortex (
.reset (l3_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l3cache_if),
.cache_perf_if (perf_l3cache_if),
`endif
.core_bus_if (per_cluster_mem_bus_if),
@ -230,23 +230,23 @@ module Vortex (
`ifdef PERF_ENABLE
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, icache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, icache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, icache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, icache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, dcache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, smem_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, smem_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, smem_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, mem_perf_if, l2cache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`ifdef L3_ENABLE
assign perf_memsys_total_if.l3cache_reads = perf_l3cache_if.reads;

18
hw/rtl/cache/VX_cache.sv vendored
View file

@ -47,7 +47,7 @@ module VX_cache #(
) (
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_cache_if,
VX_cache_perf_if.master cache_perf_if,
`endif
input wire clk,
@ -240,7 +240,7 @@ module VX_cache #(
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.bank_stalls (perf_cache_if.bank_stalls),
.bank_stalls (cache_perf_if.bank_stalls),
`endif
.core_req_valid (core_req_valid),
.core_req_rw (core_req_rw),
@ -591,13 +591,13 @@ module VX_cache #(
end
end
assign perf_cache_if.reads = perf_core_reads;
assign perf_cache_if.writes = perf_core_writes;
assign perf_cache_if.read_misses = perf_read_misses;
assign perf_cache_if.write_misses = perf_write_misses;
assign perf_cache_if.mshr_stalls = perf_mshr_stalls;
assign perf_cache_if.mem_stalls = perf_mem_stalls;
assign perf_cache_if.crsp_stalls = perf_crsp_stalls;
assign cache_perf_if.reads = perf_core_reads;
assign cache_perf_if.writes = perf_core_writes;
assign cache_perf_if.read_misses = perf_read_misses;
assign cache_perf_if.write_misses = perf_write_misses;
assign cache_perf_if.mshr_stalls = perf_mshr_stalls;
assign cache_perf_if.mem_stalls = perf_mem_stalls;
assign cache_perf_if.crsp_stalls = perf_crsp_stalls;
`endif
endmodule

10
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -57,7 +57,7 @@ module VX_cache_cluster #(
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_cache_if,
VX_cache_perf_if.master cache_perf_if,
`endif
VX_cache_bus_if.slave core_bus_if [NUM_INPUTS],
@ -74,8 +74,8 @@ module VX_cache_cluster #(
`STATIC_ASSERT(NUM_INPUTS >= NUM_CACHES, ("invalid parameter"))
`ifdef PERF_ENABLE
VX_perf_cache_if perf_cache_unit_if[NUM_CACHES]();
`PERF_CACHE_ADD (perf_cache_if, perf_cache_unit_if, NUM_CACHES);
VX_cache_perf_if perf_cache_unit_if[NUM_CACHES]();
`PERF_CACHE_ADD (cache_perf_if, perf_cache_unit_if, NUM_CACHES);
`endif
VX_mem_bus_if #(
@ -144,7 +144,7 @@ module VX_cache_cluster #(
.PASSTHRU (PASSTHRU)
) cache_wrap (
`ifdef PERF_ENABLE
.perf_cache_if (perf_cache_unit_if[i]),
.cache_perf_if (perf_cache_unit_if[i]),
`endif
.clk (clk),
@ -337,7 +337,7 @@ module VX_cache_cluster_top #(
.MEM_OUT_REG (MEM_OUT_REG)
) cache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_icache_if),
.cache_perf_if (perf_icache_if),
`endif
.clk (clk),
.reset (reset),

2
hw/rtl/interfaces/VX_perf_cache_if.sv → hw/rtl/cache/VX_cache_perf_if.sv vendored
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_perf_cache_if ();
interface VX_cache_perf_if ();
wire [`PERF_CTR_BITS-1:0] reads;
wire [`PERF_CTR_BITS-1:0] writes;

20
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -58,7 +58,7 @@ module VX_cache_wrap #(
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_cache_if,
VX_cache_perf_if.master cache_perf_if,
`endif
VX_mem_bus_if.slave core_bus_if [NUM_REQS],
@ -345,14 +345,14 @@ module VX_cache_wrap #(
assign mem_rsp_ready_b = 0;
`ifdef PERF_ENABLE
assign perf_cache_if.reads = '0;
assign perf_cache_if.writes = '0;
assign perf_cache_if.read_misses = '0;
assign perf_cache_if.write_misses = '0;
assign perf_cache_if.bank_stalls = '0;
assign perf_cache_if.mshr_stalls = '0;
assign perf_cache_if.mem_stalls = '0;
assign perf_cache_if.crsp_stalls = '0;
assign cache_perf_if.reads = '0;
assign cache_perf_if.writes = '0;
assign cache_perf_if.read_misses = '0;
assign cache_perf_if.write_misses = '0;
assign cache_perf_if.bank_stalls = '0;
assign cache_perf_if.mshr_stalls = '0;
assign cache_perf_if.mem_stalls = '0;
assign cache_perf_if.crsp_stalls = '0;
`endif
end else begin
@ -423,7 +423,7 @@ module VX_cache_wrap #(
.reset (cache_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_cache_if),
.cache_perf_if (cache_perf_if),
`endif
.core_bus_if (core_bus_wrap_if),

28
hw/rtl/core/VX_core.sv
View file

@ -34,7 +34,7 @@ module VX_core #(
input wire reset,
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_mem_perf_if.slave mem_perf_if,
`endif
VX_dcr_write_if.slave dcr_write_if,
@ -50,7 +50,7 @@ module VX_core #(
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
VX_cache_perf_if.slave perf_tcache_if,
`endif
VX_tex_bus_if.master tex_bus_if,
`endif
@ -58,7 +58,7 @@ module VX_core #(
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_cache_perf_if.slave perf_rcache_if,
`endif
VX_raster_bus_if.slave raster_bus_if,
`endif
@ -66,7 +66,7 @@ module VX_core #(
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_cache_perf_if.slave perf_ocache_if,
`endif
VX_rop_bus_if.master rop_bus_if,
`endif
@ -107,7 +107,7 @@ module VX_core #(
VX_writeback_if writeback_if();
`ifdef PERF_ENABLE
VX_perf_pipeline_if perf_pipeline_if();
VX_pipeline_perf_if pipeline_perf_if();
`endif
`RESET_RELAY (dcr_data_reset, reset);
@ -179,7 +179,7 @@ module VX_core #(
.reset (issue_reset),
`ifdef PERF_ENABLE
.perf_issue_if (perf_pipeline_if.issue),
.perf_issue_if (pipeline_perf_if.issue),
`endif
.decode_if (decode_if),
@ -205,8 +205,8 @@ module VX_core #(
.base_dcrs (base_dcrs),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_pipeline_if(perf_pipeline_if),
.mem_perf_if (mem_perf_if),
.pipeline_perf_if(pipeline_perf_if),
`endif
.dcache_bus_if (dcache_bus_if),
@ -348,12 +348,12 @@ module VX_core #(
end
end
assign perf_pipeline_if.ifetches = perf_ifetches;
assign perf_pipeline_if.loads = perf_loads;
assign perf_pipeline_if.stores = perf_stores;
assign perf_pipeline_if.load_latency = perf_dcache_lat;
assign perf_pipeline_if.ifetch_latency = perf_icache_lat;
assign perf_pipeline_if.load_latency = perf_dcache_lat;
assign pipeline_perf_if.ifetches = perf_ifetches;
assign pipeline_perf_if.loads = perf_loads;
assign pipeline_perf_if.stores = perf_stores;
assign pipeline_perf_if.load_latency = perf_dcache_lat;
assign pipeline_perf_if.ifetch_latency = perf_icache_lat;
assign pipeline_perf_if.load_latency = perf_dcache_lat;
`endif

180
hw/rtl/core/VX_csr_data.sv
View file

@ -16,20 +16,20 @@ module VX_csr_data #(
input base_dcrs_t base_dcrs,
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_perf_pipeline_if.slave perf_pipeline_if,
VX_perf_gpu_if.slave perf_gpu_if,
VX_mem_perf_if.slave mem_perf_if,
VX_pipeline_perf_if.slave pipeline_perf_if,
VX_gpu_perf_if.slave gpu_perf_if,
`ifdef EXT_TEX_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
VX_cache_perf_if.slave perf_tcache_if,
`endif
`ifdef EXT_RASTER_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_cache_perf_if.slave perf_rcache_if,
`endif
`ifdef EXT_ROP_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_cache_perf_if.slave perf_ocache_if,
`endif
`endif
@ -172,99 +172,99 @@ module VX_csr_data #(
`DCR_MPM_CLASS_CORE: begin
case (read_addr)
// PERF: pipeline
`CSR_MPM_IBUF_ST : read_data_ro_r = perf_pipeline_if.ibf_stalls[31:0];
`CSR_MPM_IBUF_ST_H : read_data_ro_r = 32'(perf_pipeline_if.ibf_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SCRB_ST : read_data_ro_r = perf_pipeline_if.scb_stalls[31:0];
`CSR_MPM_SCRB_ST_H : read_data_ro_r = 32'(perf_pipeline_if.scb_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ALU_ST : read_data_ro_r = perf_pipeline_if.alu_stalls[31:0];
`CSR_MPM_ALU_ST_H : read_data_ro_r = 32'(perf_pipeline_if.alu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LSU_ST : read_data_ro_r = perf_pipeline_if.lsu_stalls[31:0];
`CSR_MPM_LSU_ST_H : read_data_ro_r = 32'(perf_pipeline_if.lsu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_CSR_ST : read_data_ro_r = perf_pipeline_if.csr_stalls[31:0];
`CSR_MPM_CSR_ST_H : read_data_ro_r = 32'(perf_pipeline_if.csr_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_IBUF_ST : read_data_ro_r = pipeline_perf_if.ibf_stalls[31:0];
`CSR_MPM_IBUF_ST_H : read_data_ro_r = 32'(pipeline_perf_if.ibf_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SCRB_ST : read_data_ro_r = pipeline_perf_if.scb_stalls[31:0];
`CSR_MPM_SCRB_ST_H : read_data_ro_r = 32'(pipeline_perf_if.scb_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ALU_ST : read_data_ro_r = pipeline_perf_if.alu_stalls[31:0];
`CSR_MPM_ALU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.alu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LSU_ST : read_data_ro_r = pipeline_perf_if.lsu_stalls[31:0];
`CSR_MPM_LSU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.lsu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_CSR_ST : read_data_ro_r = pipeline_perf_if.csr_stalls[31:0];
`CSR_MPM_CSR_ST_H : read_data_ro_r = 32'(pipeline_perf_if.csr_stalls[`PERF_CTR_BITS-1:32]);
`ifdef EXT_F_ENABLE
`CSR_MPM_FPU_ST : read_data_ro_r = perf_pipeline_if.fpu_stalls[31:0];
`CSR_MPM_FPU_ST_H : read_data_ro_r = 32'(perf_pipeline_if.fpu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_FPU_ST : read_data_ro_r = pipeline_perf_if.fpu_stalls[31:0];
`CSR_MPM_FPU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.fpu_stalls[`PERF_CTR_BITS-1:32]);
`else
`CSR_MPM_FPU_ST : read_data_ro_r = '0;
`CSR_MPM_FPU_ST_H : read_data_ro_r = '0;
`endif
`CSR_MPM_GPU_ST : read_data_ro_r = perf_pipeline_if.gpu_stalls[31:0];
`CSR_MPM_GPU_ST_H : read_data_ro_r = 32'(perf_pipeline_if.gpu_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_GPU_ST : read_data_ro_r = pipeline_perf_if.gpu_stalls[31:0];
`CSR_MPM_GPU_ST_H : read_data_ro_r = 32'(pipeline_perf_if.gpu_stalls[`PERF_CTR_BITS-1:32]);
// PERF: memory
`CSR_MPM_IFETCHES : read_data_ro_r = perf_pipeline_if.ifetches[31:0];
`CSR_MPM_IFETCHES_H : read_data_ro_r = 32'(perf_pipeline_if.ifetches[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LOADS : read_data_ro_r = perf_pipeline_if.loads[31:0];
`CSR_MPM_LOADS_H : read_data_ro_r = 32'(perf_pipeline_if.loads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_STORES : read_data_ro_r = perf_pipeline_if.stores[31:0];
`CSR_MPM_STORES_H : read_data_ro_r = 32'(perf_pipeline_if.stores[`PERF_CTR_BITS-1:32]);
`CSR_MPM_IFETCH_LAT : read_data_ro_r = perf_pipeline_if.ifetch_latency[31:0];
`CSR_MPM_IFETCH_LAT_H : read_data_ro_r = 32'(perf_pipeline_if.ifetch_latency[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LOAD_LAT : read_data_ro_r = perf_pipeline_if.load_latency[31:0];
`CSR_MPM_LOAD_LAT_H : read_data_ro_r = 32'(perf_pipeline_if.load_latency[`PERF_CTR_BITS-1:32]);
`CSR_MPM_IFETCHES : read_data_ro_r = pipeline_perf_if.ifetches[31:0];
`CSR_MPM_IFETCHES_H : read_data_ro_r = 32'(pipeline_perf_if.ifetches[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LOADS : read_data_ro_r = pipeline_perf_if.loads[31:0];
`CSR_MPM_LOADS_H : read_data_ro_r = 32'(pipeline_perf_if.loads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_STORES : read_data_ro_r = pipeline_perf_if.stores[31:0];
`CSR_MPM_STORES_H : read_data_ro_r = 32'(pipeline_perf_if.stores[`PERF_CTR_BITS-1:32]);
`CSR_MPM_IFETCH_LAT : read_data_ro_r = pipeline_perf_if.ifetch_latency[31:0];
`CSR_MPM_IFETCH_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.ifetch_latency[`PERF_CTR_BITS-1:32]);
`CSR_MPM_LOAD_LAT : read_data_ro_r = pipeline_perf_if.load_latency[31:0];
`CSR_MPM_LOAD_LAT_H : read_data_ro_r = 32'(pipeline_perf_if.load_latency[`PERF_CTR_BITS-1:32]);
default:;
endcase
end
`DCR_MPM_CLASS_MEM: begin
case (read_addr)
// PERF: icache
`CSR_MPM_ICACHE_READS : read_data_ro_r = perf_memsys_if.icache_reads[31:0];
`CSR_MPM_ICACHE_READS_H : read_data_ro_r = 32'(perf_memsys_if.icache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ICACHE_MISS_R : read_data_ro_r = perf_memsys_if.icache_read_misses[31:0];
`CSR_MPM_ICACHE_MISS_R_H : read_data_ro_r = 32'(perf_memsys_if.icache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ICACHE_READS : read_data_ro_r = mem_perf_if.icache_reads[31:0];
`CSR_MPM_ICACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.icache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ICACHE_MISS_R : read_data_ro_r = mem_perf_if.icache_read_misses[31:0];
`CSR_MPM_ICACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.icache_read_misses[`PERF_CTR_BITS-1:32]);
// PERF: dcache
`CSR_MPM_DCACHE_READS : read_data_ro_r = perf_memsys_if.dcache_reads[31:0];
`CSR_MPM_DCACHE_READS_H : read_data_ro_r = 32'(perf_memsys_if.dcache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_WRITES : read_data_ro_r = perf_memsys_if.dcache_writes[31:0];
`CSR_MPM_DCACHE_WRITES_H : read_data_ro_r = 32'(perf_memsys_if.dcache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MISS_R : read_data_ro_r = perf_memsys_if.dcache_read_misses[31:0];
`CSR_MPM_DCACHE_MISS_R_H : read_data_ro_r = 32'(perf_memsys_if.dcache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MISS_W : read_data_ro_r = perf_memsys_if.dcache_write_misses[31:0];
`CSR_MPM_DCACHE_MISS_W_H : read_data_ro_r = 32'(perf_memsys_if.dcache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_BANK_ST : read_data_ro_r = perf_memsys_if.dcache_bank_stalls[31:0];
`CSR_MPM_DCACHE_BANK_ST_H : read_data_ro_r = 32'(perf_memsys_if.dcache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MSHR_ST : read_data_ro_r = perf_memsys_if.dcache_mshr_stalls[31:0];
`CSR_MPM_DCACHE_MSHR_ST_H : read_data_ro_r = 32'(perf_memsys_if.dcache_mshr_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_READS : read_data_ro_r = mem_perf_if.dcache_reads[31:0];
`CSR_MPM_DCACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.dcache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_WRITES : read_data_ro_r = mem_perf_if.dcache_writes[31:0];
`CSR_MPM_DCACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.dcache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MISS_R : read_data_ro_r = mem_perf_if.dcache_read_misses[31:0];
`CSR_MPM_DCACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.dcache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MISS_W : read_data_ro_r = mem_perf_if.dcache_write_misses[31:0];
`CSR_MPM_DCACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.dcache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_BANK_ST : read_data_ro_r = mem_perf_if.dcache_bank_stalls[31:0];
`CSR_MPM_DCACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_DCACHE_MSHR_ST : read_data_ro_r = mem_perf_if.dcache_mshr_stalls[31:0];
`CSR_MPM_DCACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.dcache_mshr_stalls[`PERF_CTR_BITS-1:32]);
// PERF: smem
`CSR_MPM_SMEM_READS : read_data_ro_r = perf_memsys_if.smem_reads[31:0];
`CSR_MPM_SMEM_READS_H : read_data_ro_r = 32'(perf_memsys_if.smem_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SMEM_WRITES : read_data_ro_r = perf_memsys_if.smem_writes[31:0];
`CSR_MPM_SMEM_WRITES_H : read_data_ro_r = 32'(perf_memsys_if.smem_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SMEM_BANK_ST : read_data_ro_r = perf_memsys_if.smem_bank_stalls[31:0];
`CSR_MPM_SMEM_BANK_ST_H : read_data_ro_r = 32'(perf_memsys_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SMEM_READS : read_data_ro_r = mem_perf_if.smem_reads[31:0];
`CSR_MPM_SMEM_READS_H : read_data_ro_r = 32'(mem_perf_if.smem_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SMEM_WRITES : read_data_ro_r = mem_perf_if.smem_writes[31:0];
`CSR_MPM_SMEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.smem_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_SMEM_BANK_ST : read_data_ro_r = mem_perf_if.smem_bank_stalls[31:0];
`CSR_MPM_SMEM_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.smem_bank_stalls[`PERF_CTR_BITS-1:32]);
// PERF: l2cache
`CSR_MPM_L2CACHE_READS : read_data_ro_r = perf_memsys_if.l2cache_reads[31:0];
`CSR_MPM_L2CACHE_READS_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_WRITES : read_data_ro_r = perf_memsys_if.l2cache_writes[31:0];
`CSR_MPM_L2CACHE_WRITES_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MISS_R : read_data_ro_r = perf_memsys_if.l2cache_read_misses[31:0];
`CSR_MPM_L2CACHE_MISS_R_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MISS_W : read_data_ro_r = perf_memsys_if.l2cache_write_misses[31:0];
`CSR_MPM_L2CACHE_MISS_W_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_BANK_ST : read_data_ro_r = perf_memsys_if.l2cache_bank_stalls[31:0];
`CSR_MPM_L2CACHE_BANK_ST_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MSHR_ST : read_data_ro_r = perf_memsys_if.l2cache_mshr_stalls[31:0];
`CSR_MPM_L2CACHE_MSHR_ST_H : read_data_ro_r = 32'(perf_memsys_if.l2cache_mshr_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_READS : read_data_ro_r = mem_perf_if.l2cache_reads[31:0];
`CSR_MPM_L2CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l2cache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_WRITES : read_data_ro_r = mem_perf_if.l2cache_writes[31:0];
`CSR_MPM_L2CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l2cache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MISS_R : read_data_ro_r = mem_perf_if.l2cache_read_misses[31:0];
`CSR_MPM_L2CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l2cache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MISS_W : read_data_ro_r = mem_perf_if.l2cache_write_misses[31:0];
`CSR_MPM_L2CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l2cache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l2cache_bank_stalls[31:0];
`CSR_MPM_L2CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L2CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l2cache_mshr_stalls[31:0];
`CSR_MPM_L2CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l2cache_mshr_stalls[`PERF_CTR_BITS-1:32]);
// PERF: l3cache
`CSR_MPM_L3CACHE_READS : read_data_ro_r = perf_memsys_if.l3cache_reads[31:0];
`CSR_MPM_L3CACHE_READS_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_WRITES : read_data_ro_r = perf_memsys_if.l3cache_writes[31:0];
`CSR_MPM_L3CACHE_WRITES_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MISS_R : read_data_ro_r = perf_memsys_if.l3cache_read_misses[31:0];
`CSR_MPM_L3CACHE_MISS_R_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MISS_W : read_data_ro_r = perf_memsys_if.l3cache_write_misses[31:0];
`CSR_MPM_L3CACHE_MISS_W_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_BANK_ST : read_data_ro_r = perf_memsys_if.l3cache_bank_stalls[31:0];
`CSR_MPM_L3CACHE_BANK_ST_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MSHR_ST : read_data_ro_r = perf_memsys_if.l3cache_mshr_stalls[31:0];
`CSR_MPM_L3CACHE_MSHR_ST_H : read_data_ro_r = 32'(perf_memsys_if.l3cache_mshr_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_READS : read_data_ro_r = mem_perf_if.l3cache_reads[31:0];
`CSR_MPM_L3CACHE_READS_H : read_data_ro_r = 32'(mem_perf_if.l3cache_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_WRITES : read_data_ro_r = mem_perf_if.l3cache_writes[31:0];
`CSR_MPM_L3CACHE_WRITES_H : read_data_ro_r = 32'(mem_perf_if.l3cache_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MISS_R : read_data_ro_r = mem_perf_if.l3cache_read_misses[31:0];
`CSR_MPM_L3CACHE_MISS_R_H : read_data_ro_r = 32'(mem_perf_if.l3cache_read_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MISS_W : read_data_ro_r = mem_perf_if.l3cache_write_misses[31:0];
`CSR_MPM_L3CACHE_MISS_W_H : read_data_ro_r = 32'(mem_perf_if.l3cache_write_misses[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_BANK_ST : read_data_ro_r = mem_perf_if.l3cache_bank_stalls[31:0];
`CSR_MPM_L3CACHE_BANK_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache_bank_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_L3CACHE_MSHR_ST : read_data_ro_r = mem_perf_if.l3cache_mshr_stalls[31:0];
`CSR_MPM_L3CACHE_MSHR_ST_H : read_data_ro_r = 32'(mem_perf_if.l3cache_mshr_stalls[`PERF_CTR_BITS-1:32]);
// PERF: memory
`CSR_MPM_MEM_READS : read_data_ro_r = perf_memsys_if.mem_reads[31:0];
`CSR_MPM_MEM_READS_H : read_data_ro_r = 32'(perf_memsys_if.mem_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_MEM_WRITES : read_data_ro_r = perf_memsys_if.mem_writes[31:0];
`CSR_MPM_MEM_WRITES_H : read_data_ro_r = 32'(perf_memsys_if.mem_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_MEM_LAT : read_data_ro_r = perf_memsys_if.mem_latency[31:0];
`CSR_MPM_MEM_LAT_H : read_data_ro_r = 32'(perf_memsys_if.mem_latency[`PERF_CTR_BITS-1:32]);
`CSR_MPM_MEM_READS : read_data_ro_r = mem_perf_if.mem_reads[31:0];
`CSR_MPM_MEM_READS_H : read_data_ro_r = 32'(mem_perf_if.mem_reads[`PERF_CTR_BITS-1:32]);
`CSR_MPM_MEM_WRITES : read_data_ro_r = mem_perf_if.mem_writes[31:0];
`CSR_MPM_MEM_WRITES_H : read_data_ro_r = 32'(mem_perf_if.mem_writes[`PERF_CTR_BITS-1:32]);
`CSR_MPM_MEM_LAT : read_data_ro_r = mem_perf_if.mem_latency[31:0];
`CSR_MPM_MEM_LAT_H : read_data_ro_r = 32'(mem_perf_if.mem_latency[`PERF_CTR_BITS-1:32]);
default:;
endcase
end
@ -288,8 +288,8 @@ module VX_csr_data #(
`CSR_MPM_TCACHE_MSHR_ST :read_data_ro_r = perf_tcache_if.mshr_stalls[31:0];
`CSR_MPM_TCACHE_MSHR_ST_H:read_data_ro_r = 32'(perf_tcache_if.mshr_stalls[`PERF_CTR_BITS-1:32]);
`endif
`CSR_MPM_TEX_ISSUE_ST : read_data_ro_r = perf_gpu_if.tex_stalls[31:0];
`CSR_MPM_TEX_ISSUE_ST_H : read_data_ro_r = 32'(perf_gpu_if.tex_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_TEX_ISSUE_ST : read_data_ro_r = gpu_perf_if.tex_stalls[31:0];
`CSR_MPM_TEX_ISSUE_ST_H : read_data_ro_r = 32'(gpu_perf_if.tex_stalls[`PERF_CTR_BITS-1:32]);
default:;
endcase
`endif
@ -314,8 +314,8 @@ module VX_csr_data #(
`CSR_MPM_RCACHE_MSHR_ST :read_data_ro_r = perf_rcache_if.mshr_stalls[31:0];
`CSR_MPM_RCACHE_MSHR_ST_H:read_data_ro_r = 32'(perf_rcache_if.mshr_stalls[`PERF_CTR_BITS-1:32]);
`endif
`CSR_MPM_RASTER_ISSUE_ST : read_data_ro_r = perf_gpu_if.raster_stalls[31:0];
`CSR_MPM_RASTER_ISSUE_ST_H : read_data_ro_r = 32'(perf_gpu_if.raster_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_RASTER_ISSUE_ST : read_data_ro_r = gpu_perf_if.raster_stalls[31:0];
`CSR_MPM_RASTER_ISSUE_ST_H : read_data_ro_r = 32'(gpu_perf_if.raster_stalls[`PERF_CTR_BITS-1:32]);
default:;
endcase
`endif
@ -346,8 +346,8 @@ module VX_csr_data #(
`CSR_MPM_OCACHE_MSHR_ST :read_data_ro_r = perf_ocache_if.mshr_stalls[31:0];
`CSR_MPM_OCACHE_MSHR_ST_H:read_data_ro_r = 32'(perf_ocache_if.mshr_stalls[`PERF_CTR_BITS-1:32]);
`endif
`CSR_MPM_ROP_ISSUE_ST : read_data_ro_r = perf_gpu_if.rop_stalls[31:0];
`CSR_MPM_ROP_ISSUE_ST_H : read_data_ro_r = 32'(perf_gpu_if.rop_stalls[`PERF_CTR_BITS-1:32]);
`CSR_MPM_ROP_ISSUE_ST : read_data_ro_r = gpu_perf_if.rop_stalls[31:0];
`CSR_MPM_ROP_ISSUE_ST_H : read_data_ro_r = 32'(gpu_perf_if.rop_stalls[`PERF_CTR_BITS-1:32]);
default:;
endcase
`endif
@ -373,10 +373,10 @@ module VX_csr_data #(
`ifdef PERF_ENABLE
`ifdef EXT_IMADD_ENABLE
wire [`PERF_CTR_BITS-1:0] perf_imadd_stalls = perf_gpu_if.imadd_stalls;
wire [`PERF_CTR_BITS-1:0] perf_imadd_stalls = gpu_perf_if.imadd_stalls;
`UNUSED_VAR (perf_imadd_stalls);
`endif
wire [`PERF_CTR_BITS-1:0] perf_wctl_stalls = perf_gpu_if.wctl_stalls;
wire [`PERF_CTR_BITS-1:0] perf_wctl_stalls = gpu_perf_if.wctl_stalls;
`UNUSED_VAR (perf_wctl_stalls);
`endif

18
hw/rtl/core/VX_csr_unit.sv
View file

@ -14,30 +14,30 @@ module VX_csr_unit #(
input base_dcrs_t base_dcrs,
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_perf_pipeline_if.slave perf_pipeline_if,
VX_perf_gpu_if.slave perf_gpu_if,
VX_mem_perf_if.slave mem_perf_if,
VX_pipeline_perf_if.slave pipeline_perf_if,
VX_gpu_perf_if.slave gpu_perf_if,
`endif
`ifdef EXT_TEX_ENABLE
VX_gpu_csr_if.master tex_csr_if,
`ifdef PERF_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
VX_cache_perf_if.slave perf_tcache_if,
`endif
`endif
`ifdef EXT_RASTER_ENABLE
VX_gpu_csr_if.master raster_csr_if,
`ifdef PERF_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_cache_perf_if.slave perf_rcache_if,
`endif
`endif
`ifdef EXT_ROP_ENABLE
VX_gpu_csr_if.master rop_csr_if,
`ifdef PERF_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_cache_perf_if.slave perf_ocache_if,
`endif
`endif
@ -148,9 +148,9 @@ module VX_csr_unit #(
.base_dcrs (base_dcrs),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_pipeline_if(perf_pipeline_if),
.perf_gpu_if (perf_gpu_if),
.mem_perf_if (mem_perf_if),
.pipeline_perf_if(pipeline_perf_if),
.gpu_perf_if (gpu_perf_if),
`ifdef EXT_TEX_ENABLE
.perf_tex_if (perf_tex_if),
.perf_tcache_if (perf_tcache_if),

0
hw/rtl/VX_dcr_data.sv → hw/rtl/core/VX_dcr_data.sv
View file

20
hw/rtl/core/VX_execute.sv
View file

@ -25,8 +25,8 @@ module VX_execute #(
VX_sched_csr_if.slave sched_csr_if,
`ifdef PERF_ENABLE
VX_perf_memsys_if.slave perf_memsys_if,
VX_perf_pipeline_if.slave perf_pipeline_if,
VX_mem_perf_if.slave mem_perf_if,
VX_pipeline_perf_if.slave pipeline_perf_if,
`endif
`ifdef EXT_F_ENABLE
@ -39,7 +39,7 @@ module VX_execute #(
VX_tex_bus_if.master tex_bus_if,
`ifdef PERF_ENABLE
VX_tex_perf_if.slave perf_tex_if,
VX_perf_cache_if.slave perf_tcache_if,
VX_cache_perf_if.slave perf_tcache_if,
`endif
`endif
@ -47,7 +47,7 @@ module VX_execute #(
VX_raster_bus_if.slave raster_bus_if,
`ifdef PERF_ENABLE
VX_raster_perf_if.slave perf_raster_if,
VX_perf_cache_if.slave perf_rcache_if,
VX_cache_perf_if.slave perf_rcache_if,
`endif
`endif
@ -55,7 +55,7 @@ module VX_execute #(
VX_rop_bus_if.master rop_bus_if,
`ifdef PERF_ENABLE
VX_rop_perf_if.slave perf_rop_if,
VX_perf_cache_if.slave perf_ocache_if,
VX_cache_perf_if.slave perf_ocache_if,
`endif
`endif
@ -99,7 +99,7 @@ module VX_execute #(
`endif
`ifdef PERF_ENABLE
VX_perf_gpu_if perf_gpu_if();
VX_gpu_perf_if gpu_perf_if();
`endif
`RESET_RELAY (alu_reset, reset);
@ -140,9 +140,9 @@ module VX_execute #(
.base_dcrs (base_dcrs),
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_pipeline_if(perf_pipeline_if),
.perf_gpu_if (perf_gpu_if),
.mem_perf_if (mem_perf_if),
.pipeline_perf_if(pipeline_perf_if),
.gpu_perf_if (gpu_perf_if),
`endif
.gpu_pending (gpu_pending),
@ -209,7 +209,7 @@ module VX_execute #(
.gpu_req_if (gpu_req_if),
`ifdef PERF_ENABLE
.perf_gpu_if (perf_gpu_if),
.gpu_perf_if (gpu_perf_if),
`endif
`ifdef EXT_TEX_ENABLE

0
hw/rtl/VX_gpu_types.vh → hw/rtl/core/VX_gpu_types.vh
View file

12
hw/rtl/core/VX_gpu_unit.sv
View file

@ -12,7 +12,7 @@ module VX_gpu_unit #(
input wire reset,
`ifdef PERF_ENABLE
VX_perf_gpu_if.master perf_gpu_if,
VX_gpu_perf_if.master gpu_perf_if,
`endif
// Inputs
@ -381,7 +381,7 @@ module VX_gpu_unit #(
perf_tex_stalls <= perf_tex_stalls + `PERF_CTR_BITS'(tex_agent_if.valid && ~tex_agent_if.ready);
end
end
assign perf_gpu_if.tex_stalls = perf_tex_stalls;
assign gpu_perf_if.tex_stalls = perf_tex_stalls;
`endif
`ifdef EXT_RASTER_ENABLE
reg [`PERF_CTR_BITS-1:0] perf_raster_stalls;
@ -392,7 +392,7 @@ module VX_gpu_unit #(
perf_raster_stalls <= perf_raster_stalls + `PERF_CTR_BITS'(raster_agent_if.valid && ~raster_agent_if.ready);
end
end
assign perf_gpu_if.raster_stalls = perf_raster_stalls;
assign gpu_perf_if.raster_stalls = perf_raster_stalls;
`endif
`ifdef EXT_ROP_ENABLE
reg [`PERF_CTR_BITS-1:0] perf_rop_stalls;
@ -403,7 +403,7 @@ module VX_gpu_unit #(
perf_rop_stalls <= perf_rop_stalls + `PERF_CTR_BITS'(rop_agent_if.valid && ~rop_agent_if.ready);
end
end
assign perf_gpu_if.rop_stalls = perf_rop_stalls;
assign gpu_perf_if.rop_stalls = perf_rop_stalls;
`endif
`ifdef EXT_IMADD_ENABLE
reg [`PERF_CTR_BITS-1:0] perf_imadd_stalls;
@ -414,7 +414,7 @@ module VX_gpu_unit #(
perf_imadd_stalls <= perf_imadd_stalls + `PERF_CTR_BITS'(imadd_valid_in && ~imadd_ready_in);
end
end
assign perf_gpu_if.imadd_stalls = perf_imadd_stalls;
assign gpu_perf_if.imadd_stalls = perf_imadd_stalls;
`endif
reg [`PERF_CTR_BITS-1:0] perf_wctl_stalls;
always @(posedge clk) begin
@ -424,7 +424,7 @@ module VX_gpu_unit #(
perf_wctl_stalls <= perf_wctl_stalls + `PERF_CTR_BITS'(wctl_req_valid && ~wctl_req_ready);
end
end
assign perf_gpu_if.wctl_stalls = perf_wctl_stalls;
assign gpu_perf_if.wctl_stalls = perf_wctl_stalls;
`endif
endmodule

2
hw/rtl/core/VX_issue.sv
View file

@ -12,7 +12,7 @@ module VX_issue #(
input wire reset,
`ifdef PERF_ENABLE
VX_perf_pipeline_if.issue perf_issue_if,
VX_pipeline_perf_if.issue perf_issue_if,
`endif
VX_decode_if.slave decode_if,

0
hw/rtl/VX_trace_info.vh → hw/rtl/core/VX_trace_info.vh
View file

2
hw/rtl/interfaces/VX_perf_gpu_if.sv → hw/rtl/interfaces/VX_gpu_perf_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_perf_gpu_if ();
interface VX_gpu_perf_if ();
`ifdef EXT_TEX_ENABLE
wire [`PERF_CTR_BITS-1:0] tex_stalls;

2
hw/rtl/interfaces/VX_perf_pipeline_if.sv → hw/rtl/interfaces/VX_pipeline_perf_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_perf_pipeline_if ();
interface VX_pipeline_perf_if ();
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;

0
hw/rtl/VX_gbar_arb.sv → hw/rtl/mem/VX_gbar_arb.sv
View file

0
hw/rtl/interfaces/VX_gbar_bus_if.sv → hw/rtl/mem/VX_gbar_bus_if.sv
View file

0
hw/rtl/VX_gbar_unit.sv → hw/rtl/mem/VX_gbar_unit.sv
View file

0
hw/rtl/VX_mem_arb.sv → hw/rtl/mem/VX_mem_arb.sv
View file

0
hw/rtl/interfaces/VX_mem_bus_if.sv → hw/rtl/mem/VX_mem_bus_if.sv
View file

2
hw/rtl/interfaces/VX_perf_memsys_if.sv → hw/rtl/mem/VX_mem_perf_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_perf_memsys_if ();
interface VX_mem_perf_if ();
wire [`PERF_CTR_BITS-1:0] icache_reads;
wire [`PERF_CTR_BITS-1:0] icache_read_misses;

100
hw/rtl/VX_mem_unit.sv → hw/rtl/mem/VX_mem_unit.sv
View file

@ -12,7 +12,7 @@ module VX_mem_unit # (
input wire reset,
`ifdef PERF_ENABLE
VX_perf_memsys_if.master perf_memsys_if,
VX_mem_perf_if.master mem_perf_if,
`endif
VX_cache_bus_if.slave icache_bus_if [`NUM_SOCKETS],
@ -21,21 +21,21 @@ module VX_mem_unit # (
`ifdef EXT_TEX_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_tcache_if,
VX_cache_perf_if.master perf_tcache_if,
`endif
VX_cache_bus_if.slave tcache_bus_if [`NUM_TEX_UNITS],
`endif
`ifdef EXT_RASTER_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_rcache_if,
VX_cache_perf_if.master perf_rcache_if,
`endif
VX_cache_bus_if.slave rcache_bus_if [`NUM_RASTER_UNITS],
`endif
`ifdef EXT_ROP_ENABLE
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_ocache_if,
VX_cache_perf_if.master perf_ocache_if,
`endif
VX_cache_bus_if.slave ocache_bus_if [`NUM_ROP_UNITS],
`endif
@ -44,10 +44,10 @@ module VX_mem_unit # (
);
`ifdef PERF_ENABLE
VX_perf_cache_if perf_icache_if();
VX_perf_cache_if perf_dcache_if();
VX_perf_cache_if perf_smem_if();
VX_perf_cache_if perf_l2cache_if();
VX_cache_perf_if perf_icache_if();
VX_cache_perf_if perf_dcache_if();
VX_cache_perf_if perf_smem_if();
VX_cache_perf_if perf_l2cache_if();
`endif
/////////////////////////////// I-Cache ///////////////////////////////////
@ -82,7 +82,7 @@ module VX_mem_unit # (
.MEM_OUT_REG (3)
) icache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_icache_if),
.cache_perf_if (perf_icache_if),
`endif
.clk (clk),
.reset (icache_reset),
@ -130,7 +130,7 @@ module VX_mem_unit # (
.MEM_OUT_REG (3)
) dcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_dcache_if),
.cache_perf_if (perf_dcache_if),
`endif
.clk (clk),
@ -210,7 +210,7 @@ module VX_mem_unit # (
.reset (smem_reset),
`ifdef PERF_ENABLE
.perf_cache_if(perf_smem_if),
.cache_perf_if(perf_smem_if),
`endif
// Core request
@ -274,7 +274,7 @@ module VX_mem_unit # (
.MEM_OUT_REG (3)
) tcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_tcache_if),
.cache_perf_if (perf_tcache_if),
`endif
.clk (clk),
.reset (tcache_reset),
@ -320,7 +320,7 @@ module VX_mem_unit # (
.MEM_OUT_REG (3)
) ocache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_ocache_if),
.cache_perf_if (perf_ocache_if),
`endif
.clk (clk),
.reset (ocache_reset),
@ -367,7 +367,7 @@ module VX_mem_unit # (
.MEM_OUT_REG (3)
) rcache (
`ifdef PERF_ENABLE
.perf_cache_if (perf_rcache_if),
.cache_perf_if (perf_rcache_if),
`endif
.clk (clk),
.reset (rcache_reset),
@ -435,7 +435,7 @@ module VX_mem_unit # (
.clk (clk),
.reset (l2_reset),
`ifdef PERF_ENABLE
.perf_cache_if (perf_l2cache_if),
.cache_perf_if (perf_l2cache_if),
`endif
.core_bus_if (l2_mem_bus_if),
.mem_bus_if (mem_bus_if)
@ -446,52 +446,52 @@ module VX_mem_unit # (
`UNUSED_VAR (perf_dcache_if.mem_stalls)
`UNUSED_VAR (perf_dcache_if.crsp_stalls)
assign perf_memsys_if.icache_reads = perf_icache_if.reads;
assign perf_memsys_if.icache_read_misses = perf_icache_if.read_misses;
assign mem_perf_if.icache_reads = perf_icache_if.reads;
assign mem_perf_if.icache_read_misses = perf_icache_if.read_misses;
assign perf_memsys_if.dcache_reads = perf_dcache_if.reads;
assign perf_memsys_if.dcache_writes = perf_dcache_if.writes;
assign perf_memsys_if.dcache_read_misses = perf_dcache_if.read_misses;
assign perf_memsys_if.dcache_write_misses= perf_dcache_if.write_misses;
assign perf_memsys_if.dcache_bank_stalls = perf_dcache_if.bank_stalls;
assign perf_memsys_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls;
assign mem_perf_if.dcache_reads = perf_dcache_if.reads;
assign mem_perf_if.dcache_writes = perf_dcache_if.writes;
assign mem_perf_if.dcache_read_misses = perf_dcache_if.read_misses;
assign mem_perf_if.dcache_write_misses= perf_dcache_if.write_misses;
assign mem_perf_if.dcache_bank_stalls = perf_dcache_if.bank_stalls;
assign mem_perf_if.dcache_mshr_stalls = perf_dcache_if.mshr_stalls;
`ifdef SM_ENABLE
assign perf_memsys_if.smem_reads = perf_smem_if.reads;
assign perf_memsys_if.smem_writes = perf_smem_if.writes;
assign perf_memsys_if.smem_bank_stalls = perf_smem_if.bank_stalls;
assign mem_perf_if.smem_reads = perf_smem_if.reads;
assign mem_perf_if.smem_writes = perf_smem_if.writes;
assign mem_perf_if.smem_bank_stalls = perf_smem_if.bank_stalls;
`else
assign perf_memsys_if.smem_reads = '0;
assign perf_memsys_if.smem_writes = '0;
assign perf_memsys_if.smem_bank_stalls = '0;
assign mem_perf_if.smem_reads = '0;
assign mem_perf_if.smem_writes = '0;
assign mem_perf_if.smem_bank_stalls = '0;
`endif
`ifdef L2_ENABLE
assign perf_memsys_if.l2cache_reads = perf_l2cache_if.reads;
assign perf_memsys_if.l2cache_writes = perf_l2cache_if.writes;
assign perf_memsys_if.l2cache_read_misses = perf_l2cache_if.read_misses;
assign perf_memsys_if.l2cache_write_misses= perf_l2cache_if.write_misses;
assign perf_memsys_if.l2cache_bank_stalls = perf_l2cache_if.bank_stalls;
assign perf_memsys_if.l2cache_mshr_stalls = perf_l2cache_if.mshr_stalls;
assign mem_perf_if.l2cache_reads = perf_l2cache_if.reads;
assign mem_perf_if.l2cache_writes = perf_l2cache_if.writes;
assign mem_perf_if.l2cache_read_misses = perf_l2cache_if.read_misses;
assign mem_perf_if.l2cache_write_misses= perf_l2cache_if.write_misses;
assign mem_perf_if.l2cache_bank_stalls = perf_l2cache_if.bank_stalls;
assign mem_perf_if.l2cache_mshr_stalls = perf_l2cache_if.mshr_stalls;
`else
assign perf_memsys_if.l2cache_reads = '0;
assign perf_memsys_if.l2cache_writes = '0;
assign perf_memsys_if.l2cache_read_misses = '0;
assign perf_memsys_if.l2cache_write_misses= '0;
assign perf_memsys_if.l2cache_bank_stalls = '0;
assign perf_memsys_if.l2cache_mshr_stalls = '0;
assign mem_perf_if.l2cache_reads = '0;
assign mem_perf_if.l2cache_writes = '0;
assign mem_perf_if.l2cache_read_misses = '0;
assign mem_perf_if.l2cache_write_misses= '0;
assign mem_perf_if.l2cache_bank_stalls = '0;
assign mem_perf_if.l2cache_mshr_stalls = '0;
`endif
assign perf_memsys_if.l3cache_reads = '0;
assign perf_memsys_if.l3cache_writes = '0;
assign perf_memsys_if.l3cache_read_misses = '0;
assign perf_memsys_if.l3cache_write_misses= '0;
assign perf_memsys_if.l3cache_bank_stalls = '0;
assign perf_memsys_if.l3cache_mshr_stalls = '0;
assign mem_perf_if.l3cache_reads = '0;
assign mem_perf_if.l3cache_writes = '0;
assign mem_perf_if.l3cache_read_misses = '0;
assign mem_perf_if.l3cache_write_misses= '0;
assign mem_perf_if.l3cache_bank_stalls = '0;
assign mem_perf_if.l3cache_mshr_stalls = '0;
assign perf_memsys_if.mem_reads = '0;
assign perf_memsys_if.mem_writes = '0;
assign perf_memsys_if.mem_latency = '0;
assign mem_perf_if.mem_reads = '0;
assign mem_perf_if.mem_writes = '0;
assign mem_perf_if.mem_latency = '0;
`endif

18
hw/rtl/cache/VX_shared_mem.sv → hw/rtl/mem/VX_shared_mem.sv
View file

@ -30,7 +30,7 @@ module VX_shared_mem #(
// PERF
`ifdef PERF_ENABLE
VX_perf_cache_if.master perf_cache_if,
VX_cache_perf_if.master cache_perf_if,
`endif
// Core request
@ -80,7 +80,7 @@ module VX_shared_mem #(
.clk (clk),
.reset (reset),
`ifdef PERF_ENABLE
.bank_stalls (perf_cache_if.bank_stalls),
.bank_stalls (cache_perf_if.bank_stalls),
`endif
.core_req_valid (req_valid),
.core_req_rw (req_rw),
@ -245,13 +245,13 @@ module VX_shared_mem #(
end
end
assign perf_cache_if.reads = perf_reads;
assign perf_cache_if.writes = perf_writes;
assign perf_cache_if.read_misses = '0;
assign perf_cache_if.write_misses = '0;
assign perf_cache_if.mshr_stalls = '0;
assign perf_cache_if.mem_stalls = '0;
assign perf_cache_if.crsp_stalls = perf_crsp_stalls;
assign cache_perf_if.reads = perf_reads;
assign cache_perf_if.writes = perf_writes;
assign cache_perf_if.read_misses = '0;
assign cache_perf_if.write_misses = '0;
assign cache_perf_if.mshr_stalls = '0;
assign cache_perf_if.mem_stalls = '0;
assign cache_perf_if.crsp_stalls = perf_crsp_stalls;
`endif

0
hw/rtl/cache/VX_smem_switch.sv → hw/rtl/mem/VX_smem_switch.sv
View file

2
hw/syn/altera/opae/Makefile
View file

@ -64,7 +64,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/inclu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
# compilation flags

2
hw/syn/altera/quartus/core/Makefile
View file

@ -8,4 +8,4 @@ CONFIGS += -DEXT_GFX_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

2
hw/syn/altera/quartus/top-gfx/Makefile
View file

@ -18,4 +18,4 @@ CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/top/Makefile
View file

@ -15,4 +15,4 @@ CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/unittest/Makefile
View file

@ -6,4 +6,4 @@ include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/vortex-gfx/Makefile
View file

@ -22,4 +22,4 @@ CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

2
hw/syn/altera/quartus/vortex/Makefile
View file

@ -18,4 +18,4 @@ CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/xilinx/test/Makefile
View file

@ -10,7 +10,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/inclu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -Iproject_1_files

2
hw/syn/xilinx/xrt/Makefile
View file

@ -83,7 +83,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/inclu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR)
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
# Kernel compiler global settings

2
hw/syn/yosys/Makefile
View file

@ -5,7 +5,7 @@ RTL_DIR = ../../rtl
DEFINES = -DNDEBUG -DSYNTHESIS -DEXT_F_DISABLE -DNUM_CORES=1 -DNUM_THREADS=2 -DNUM_WARPS=2 -DMEM_BLOCK_SIZE=64
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
# Build targets
all: build

2
sim/opaesim/Makefile
View file

@ -50,7 +50,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/inclu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache $(FPU_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -I$(AFU_DIR) -I$(AFU_DIR)/ccip

2
sim/rtlsim/Makefile
View file

@ -36,7 +36,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/inclu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp