github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-22 21:09:15 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2023-04-06 18:12:46 -04:00
parent 31a2539ecd
commit d67deb53c4
10 changed files with 20 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/rtl/VX_platform.vh
View file

@ -1,10 +1,6 @@
`ifndef VX_PLATFORM_VH
`define VX_PLATFORM_VH
`ifndef NOGLOBALS
`include "globals.vh"
`endif
`ifndef SYNTHESIS
`include "util_dpi.vh"
`endif

2
hw/scripts/scope.json
View file

@ -11,8 +11,8 @@
"../rtl/libs"
],
"includes":[
"../rtl/VX_config.vh",
"../rtl/VX_platform.vh",
"../rtl/VX_config.vh",
"../rtl/VX_define.vh",
"../rtl/VX_gpu_types.vh",
"../rtl/fpu_unit/VX_fpu_types.vh",

2
hw/syn/altera/opae/Makefile
View file

@ -59,7 +59,7 @@ RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interface
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
# compilation flags
CFLAGS += -DSYNTHESIS -DQUARTUS -DNOGLOBALS
CFLAGS += -DSYNTHESIS -DQUARTUS
CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)

1
hw/syn/altera/quartus/project.tcl
View file

@ -37,7 +37,6 @@ set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
set_global_assignment -name VERILOG_MACRO QUARTUS
set_global_assignment -name VERILOG_MACRO SYNTHESIS
set_global_assignment -name VERILOG_MACRO NOGLOBALS
set_global_assignment -name MESSAGE_DISABLE 16818
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

11
hw/syn/xilinx/test/Makefile
View file

@ -14,9 +14,18 @@ RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -Iproject_1_files
# compilation flags
CFLAGS += -DSYNTHESIS -DVIVADO -DNOGLOBALS
CFLAGS += -DNDEBUG -DSYNTHESIS -DVIVADO
CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)
CFLAGS += -DEXT_F_DISABLE
#CFLAGS += -DEXT_GFX_ENABLE
#CFLAGS += -DNUM_CORES 4
# update memory layout for 2MB RAM
CFLAGS += -DSTARTUP_ADDR=32'h80000
CFLAGS += -DIO_BASE_ADDR=32'hFF000
CFLAGS += -DIO_ADDR_SIZE=(32'hFFFFF-`IO_BASE_ADDR+1)
CFLAGS += -DIO_COUT_ADDR=(32'hFFFFF-`MEM_BLOCK_SIZE+1)
COE_FILE := $(realpath project_1_files)/kernel.bin.coe
ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')

18
hw/syn/xilinx/test/project_1_files/globals.vh
View file

@ -1,18 +0,0 @@
`ifndef GLOBALS_VH
`define GLOBALS_VH
`define SYNTHESIS
`define NDEBUG
`define VIVADO
`define EXT_F_DISABLE
//`define EXT_GFX_ENABLE
//`define NUM_CORES 4
`define STARTUP_ADDR 32'h80000
`define IO_BASE_ADDR 32'hFF000
`define IO_ADDR_SIZE (32'hFFFFF - `IO_BASE_ADDR + 1)
`define IO_COUT_ADDR (32'hFFFFF - `MEM_BLOCK_SIZE + 1)
`endif // GLOBALS_VH

2
hw/syn/xilinx/xrt/Makefile
View file

@ -83,7 +83,7 @@ RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
# compilation flags
CFLAGS += -DSYNTHESIS -DVIVADO -DNOGLOBALS
CFLAGS += -DSYNTHESIS -DVIVADO
CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)

8
runtime/opae/Makefile
View file

@ -28,13 +28,15 @@ ifdef DEBUG
CXXFLAGS += -g -O0
else
CXXFLAGS += -O2 -DNDEBUG
SCOPE_FLAGS += -D NDEBUG
endif
# Enable scope analyzer
ifdef SCOPE
CXXFLAGS += -DSCOPE
SRCS += scope.cpp
SCOPE_H = scope-defs.h
SCOPE_H = scope-defs.h
SCOPE_FLAGS += -D SCOPE
endif
# Enable perf counters
@ -47,7 +49,7 @@ PROJECT = libvortex.so
all: $(PROJECT)
scope-defs.h: $(SCRIPT_DIR)/scope.json
$(SCRIPT_DIR)/scope.py $(CONFIGS) -D NOGLOBALS -D SIMULATION -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json
$(SCRIPT_DIR)/scope.py $(CONFIGS) $(SCOPE_FLAGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json
# generate scope data
scope: scope-defs.h
@ -59,7 +61,7 @@ endif
$(CXX) $(CXXFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT)
clean:
rm -rf $(PROJECT) *.o scope-defs.h
rm -rf $(PROJECT) *.o scope-defs.h $(RTL_DIR)/scope-defs.vh
ifeq ($(TARGET), opaesim)
$(MAKE) -C $(OPAESIM_DIR) clean
endif

2
sim/opaesim/Makefile
View file

@ -49,7 +49,7 @@ VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP)
VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += -DSIMULATION -DNOGLOBALS
VL_FLAGS += -DSIMULATION
VL_FLAGS += verilator.vlt
VL_FLAGS += $(RTL_INCLUDE)

2
sim/rtlsim/Makefile
View file

@ -51,7 +51,7 @@ VL_FLAGS = --exe --cc $(TOP) --top-module $(TOP)
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic
VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += -DSIMULATION -DNOGLOBALS
VL_FLAGS += -DSIMULATION
VL_FLAGS += verilator.vlt
VL_FLAGS += $(RTL_INCLUDE)