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https://github.com/vortexgpgpu/vortex.git
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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wgulian3
parent
a32d654263
commit
d71f8fcc73
2 changed files with 144 additions and 105 deletions
144
rtl/VX_alu.v
144
rtl/VX_alu.v
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@ -16,6 +16,80 @@ module VX_alu(
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localparam div_pipeline_len = 3;
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wire[31:0] unsigned_div_result;
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wire[31:0] unsigned_rem_result;
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wire[31:0] signed_div_result;
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wire[31:0] signed_rem_result;
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) unsigned_div (
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(unsigned_div_result),
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.remainder(unsigned_rem_result)
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);
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.NREP("SIGNED"),
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.DREP("SIGNED"),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) signed_div (
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(signed_div_result),
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.remainder(signed_rem_result)
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);
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reg [15:0] curr_inst_delay;
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reg [15:0] inst_delay;
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reg inst_was_stalling;
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wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0;
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assign out_alu_stall = inst_delay_stall;
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always @(*) begin
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case(in_alu_op)
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`DIV,
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`DIVU,
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`REM,
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`REMU: curr_inst_delay = div_pipeline_len;
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default: curr_inst_delay = 0;
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endcase // in_alu_op
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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inst_delay <= 0;
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inst_was_stalling <= 0;
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end
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else if (inst_delay_stall) begin
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if (inst_was_stalling) begin
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if (inst_delay > 0)
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inst_delay <= inst_delay - 1;
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end
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else begin
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inst_was_stalling <= 1;
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inst_delay <= curr_inst_delay - 1;
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end
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end
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else begin
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inst_was_stalling <= 0;
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end
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end
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`ifdef SYN_FUNC
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wire which_in2;
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@ -24,15 +98,6 @@ module VX_alu(
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wire[63:0] ALU_in1_mult;
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wire[63:0] ALU_in2_mult;
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wire[31:0] upper_immed;
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wire[31:0] unsigned_div_result;
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wire[31:0] unsigned_rem_result;
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wire[31:0] signed_div_result;
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wire[31:0] signed_rem_result;
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reg [15:0] inst_delay;
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reg [15:0] inst_delay_count;
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assign out_alu_stall = inst_delay != 0 || inst_delay_count != 0;
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assign which_in2 = in_rs2_src == `RS2_IMMED;
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@ -41,39 +106,6 @@ module VX_alu(
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assign upper_immed = {in_upper_immed, {12{1'b0}}};
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) unsigned_div (
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(unsigned_div_result),
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.remainder(unsigned_rem_result)
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);
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.NREP("SIGNED"),
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.DREP("SIGNED"),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) signed_div (
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.clock(clk),
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.aclr(0),
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.clken(1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(signed_div_result),
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.remainder(signed_rem_result)
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);
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//always @(posedge `MUL) begin
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@ -116,25 +148,6 @@ module VX_alu(
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endcase // in_alu_op
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end
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always @(*) begin
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case(in_alu_op)
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`DIV,
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`DIVU,
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`REM,
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`REMU: inst_delay = div_pipeline_len;
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default: inst_delay = 0;
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endcase // in_alu_op
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end
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always @(posedge clk or posedge reset) begin
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if (reset)
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inst_delay_count <= 0;
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else if (inst_delay_count > 0)
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inst_delay_count <= inst_delay_count - 1;
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else if (inst_delay != 0)
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inst_delay_count <= inst_delay - 1;
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end
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`else
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wire which_in2;
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@ -186,10 +199,11 @@ module VX_alu(
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`MULH: out_alu_result = mult_signed_result[63:32];
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`MULHSU: out_alu_result = mult_signed_un_result[63:32];
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`MULHU: out_alu_result = mult_unsigned_result[63:32];
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
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`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
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// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
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`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
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default: out_alu_result = 32'h0;
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endcase // in_alu_op
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end
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@ -13,8 +13,8 @@ module VX_divide
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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output [WIDTHN-1:0] quotient,
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output [WIDTHD-1:0] remainder
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output reg [WIDTHN-1:0] quotient,
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output reg [WIDTHD-1:0] remainder
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);
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// synthesis read_comments_as_HDL on
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@ -53,61 +53,86 @@ module VX_divide
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);
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end
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else if (PIPELINE == 0) begin
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if (NREP == "SIGNED") begin
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assign quotient = $signed($signed(numer)/$signed(denom));
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assign remainder = $signed($signed(numer)%$signed(denom));
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end
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else begin
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assign quotient = numer/denom;
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assign remainder = numer%denom;
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end
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end
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else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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end else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[pipe_stage+1] <= 0;
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denom_pipe[pipe_stage+1] <= 0;
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end
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else if (clken) begin
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numer_pipe[pipe_stage+1] <= numer_pipe[pipe_stage];
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denom_pipe[pipe_stage+1] <= denom_pipe[pipe_stage];
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end
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end
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end
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genvar pipe_stage;
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for (pipe_stage = 0; pipe_stage < PIPELINE-1; pipe_stage = pipe_stage+1) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[pipe_stage+1] <= 0;
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denom_pipe[pipe_stage+1] <= 0;
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numer_pipe[0] <= 0;
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denom_pipe[0] <= 0;
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end
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else if (clken) begin
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numer_pipe[pipe_stage+1] <= numer_pipe[pipe_stage];
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denom_pipe[pipe_stage+1] <= denom_pipe[pipe_stage];
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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end
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end
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[0] <= 0;
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denom_pipe[0] <= 0;
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end
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else if (clken) begin
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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end
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end
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wire [WIDTHN-1:0] numer_pipe_end;
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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wire [WIDTHD-1:0] denom_pipe_end;
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (NREP == "SIGNED") begin
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assign quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
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assign remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
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/*VX_divide_internal_signed #(
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.WIDTHN,
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.WIDTHD
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)div(
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.numer(numer_pipe_end),
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.denom(denom_pipe_end),
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.quotient,
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.remainder
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);*/
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = 32'hffffffff;
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remainder = numer_pipe_end;
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end
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else if (denom_pipe_end == 32'hffffffff && numer_pipe_end == 32'h80000000) begin
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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quotient = 0;
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remainder = 0;
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end
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else begin
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quotient = $signed($signed(numer_pipe_end)/$signed(denom_pipe_end));
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remainder = $signed($signed(numer_pipe_end)%$signed(denom_pipe_end));
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end
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end
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end
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else begin
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assign quotient = numer_pipe_end/denom_pipe_end;
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assign remainder = numer_pipe_end%denom_pipe_end;
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assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
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assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
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end
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end
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endgenerate
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endmodule: VX_divide
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endmodule : VX_divide
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