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minor update

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This commit is contained in:
Blaise Tine 2024-09-02 02:33:30 -07:00
parent 32636fac70
commit d7eae0c886
7 changed files with 19 additions and 23 deletions
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2
hw/rtl/VX_platform.vh
View file

@ -158,7 +158,7 @@
`define MAX_FANOUT 8
`define IF_DATA_SIZE(x) $bits(x.data)
`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *)
`define NO_RW_RAM_CHECK (* ramstyle = "no_rw_check" *)
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
`define DISABLE_BRAM (* ramstyle = "logic" *)
`define PRESERVE_NET (* preserve *)
`elsif VIVADO

4
hw/rtl/cache/VX_bank_flush.sv vendored
View file

@ -117,8 +117,8 @@ module VX_bank_flush #(
VX_decoder #(
.N (`CS_WAY_SEL_BITS)
) ctr_decoder (
.shift_in (counter_r[`CS_LINE_SEL_BITS +: `CS_WAY_SEL_BITS]),
.data_in (1'b1),
.data_in (counter_r[`CS_LINE_SEL_BITS +: `CS_WAY_SEL_BITS]),
.valid_in (1'b1),
.data_out (flush_way)
);
end else begin

4
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -68,8 +68,8 @@ module VX_cyclic_arbiter #(
VX_decoder #(
.N (LOG_NUM_REQS)
) grant_decoder (
.shift_in (grant_index),
.data_in (1'b1),
.data_in (grant_index),
.valid_in (1'b1),
.data_out (grant_onehot_w)
);

12
hw/rtl/libs/VX_decoder.sv
View file

@ -20,26 +20,22 @@
module VX_decoder #(
parameter N = 1,
parameter M = 1,
`ifdef VIVADO
parameter MODEL = 1,
`else
parameter MODEL = 0,
`endif
parameter D = 1 << N
) (
input wire [N-1:0] shift_in,
input wire [M-1:0] data_in,
input wire [N-1:0] data_in,
input wire [M-1:0] valid_in,
output wire [D-1:0][M-1:0] data_out
);
if (MODEL == 1) begin
reg [D-1:0][M-1:0] data_out_w;
always @(*) begin
data_out_w = '0;
data_out_w[shift_in] = data_in;
data_out_w[data_in] = valid_in;
end
assign data_out = data_out_w;
end else begin
assign data_out = (D*M)'(data_in) << (shift_in * M);
assign data_out = (D*M)'(valid_in) << (data_in * M);
end
endmodule

8
hw/rtl/libs/VX_mem_adapter.sv
View file

@ -101,8 +101,8 @@ module VX_mem_adapter #(
.N (D),
.M (SRC_DATA_WIDTH/8)
) req_be_dec (
.shift_in (req_idx),
.data_in (mem_req_byteen_in),
.data_in (req_idx),
.valid_in (mem_req_byteen_in),
.data_out (mem_req_byteen_out_w)
);
@ -110,8 +110,8 @@ module VX_mem_adapter #(
.N (D),
.M (SRC_DATA_WIDTH)
) req_data_dec (
.shift_in (req_idx),
.data_in (mem_req_data_in),
.data_in (req_idx),
.valid_in (mem_req_data_in),
.data_out (mem_req_data_out_w)
);

4
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -483,8 +483,8 @@ module VX_rr_arbiter #(
VX_decoder #(
.N (LOG_NUM_REQS)
) grant_decoder (
.shift_in (grant_index),
.data_in (grant_valid),
.data_in (grant_index),
.valid_in (grant_valid),
.data_out (grant_onehot)
);

8
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -75,8 +75,8 @@ module VX_stream_xbar #(
VX_decoder #(
.N (OUT_WIDTH)
) sel_in_decoder (
.shift_in (sel_in[i]),
.data_in (valid_in[i]),
.data_in (sel_in[i]),
.valid_in (valid_in[i]),
.data_out (per_output_valid_in[i])
);
assign ready_in[i] = | per_output_ready_in_w[i];
@ -139,8 +139,8 @@ module VX_stream_xbar #(
VX_decoder #(
.N (OUT_WIDTH)
) sel_in_decoder (
.shift_in (sel_in[0]),
.data_in (valid_in[0]),
.data_in (sel_in[0]),
.valid_in (valid_in[0]),
.data_out (valid_out_w)
);