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changes vector

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This commit is contained in:
proshan3 2019-11-22 12:52:35 -05:00
parent 269376883e
commit d7fa303282
8 changed files with 65 additions and 14 deletions
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2
runtime/mains/vector_test/vx_vector_main.dump
View file

@ -60,7 +60,7 @@ Disassembly of section .text:
800000b0: 00008067 ret
800000b4 <vx_vec_test>:
800000b4: 00200513 li a0,2
800000b4: 00500513 li a0,5
800000b8: 008572d7 vsetvli t0,a0,e32,m1,d1
800000bc: 00a00513 li a0,10
800000c0: 00a5a023 sw a0,0(a1)

BIN
runtime/mains/vector_test/vx_vector_main.elf
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Binary file not shown.

2
runtime/mains/vector_test/vx_vector_main.hex
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@ -10,7 +10,7 @@
:100080009396A601732600029315A6001316260068
:1000900037F1FF6F3301B1403301D1403301C1006B
:1000A000F326100263860600130500006B000500AE
:1000B0006780000013052000D77285001305A0009B
:1000B0006780000013055000D77285001305A0006B
:1000C00023A0A50023A0A50287E0051213061000B7
:1000D00023A0C6001306000023A0C60207E00612F4
:1000E00057A0016AD7801000A7E0050287E2051239

36
simX/core.cpp
View file

@ -41,6 +41,9 @@
trace_inst.rs1 = -1; \
trace_inst.rs2 = -1; \
trace_inst.rd = -1; \
trace_inst.vs1 = -1; \
trace_inst.vs2 = -1; \
trace_inst.vd = -1; \
trace_inst.is_lw = false; \
trace_inst.is_sw = false; \
trace_inst.mem_addresses = new unsigned[a.getNThds()]; \
@ -58,6 +61,9 @@
drain.rs1 = source.rs1; \
drain.rs2 = source.rs2; \
drain.rd = source.rd; \
drain.vs1 = source.vs1; \
drain.vs2 = source.vs2; \
drain.vd = source.vd; \
drain.is_lw = source.is_lw; \
drain.is_sw = source.is_sw; \
for (int tid = 0; tid < a.getNThds(); tid++) drain.mem_addresses[tid] = source.mem_addresses[tid]; \
@ -120,6 +126,11 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
}
}
for(int i = 0; i < 32; i++)
{
vecRenameTable[i] = true;
}
cache_simulator = new Vcache_simX;
m_trace = new VerilatedVcdC;
@ -474,9 +485,19 @@ void Core::load_store()
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
}
if(inst_in_scheduler.vs1 > 0)
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs1];
}
if(inst_in_scheduler.vs2 > 0)
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs2];
}
if (scheduler_srcs_ready)
{
if (inst_in_scheduler.rd != -1) renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
if (inst_in_scheduler.rd != -1) vecRenameTable[inst_in_scheduler.vd] = false;
CPY_TRACE(inst_in_lsu, inst_in_scheduler);
INIT_TRACE(inst_in_scheduler);
}
@ -524,6 +545,15 @@ void Core::execute_unit()
scheduler_srcs_ready = scheduler_srcs_ready && renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2];
// cout << "Rename RS2: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2] << " wid: " << inst_in_scheduler.wid << '\n';
}
if(inst_in_scheduler.vs1 > 0)
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs1];
}
if(inst_in_scheduler.vs2 > 0)
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs2];
}
if (scheduler_srcs_ready)
{
@ -531,6 +561,9 @@ void Core::execute_unit()
// cout << "rename setting rd: " << inst_in_scheduler.rd << " to not useabel wid: " << inst_in_scheduler.wid << '\n';
renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
}
if(inst_in_scheduler.vd != -1) {
vecRenameTable[inst_in_scheduler.vd] = false;
}
CPY_TRACE(inst_in_exe, inst_in_scheduler);
INIT_TRACE(inst_in_scheduler);
}
@ -557,6 +590,7 @@ void Core::writeback()
if (inst_in_wb.rd > 0) renameTable[inst_in_wb.wid][inst_in_wb.rd] = true;
if (inst_in_wb.vd > 0) vecRenameTable[inst_in_wb.vd] = true;
if (inst_in_wb.stall_warp)
{
@ -585,7 +619,7 @@ void Core::writeback()
}
else
{
if ((inst_in_lsu.rd > 0) && (inst_in_lsu.mem_stall_cycles == 0))
if (((inst_in_lsu.rd > 0) || (inst_in_lsu.vd > 0)) && (inst_in_lsu.mem_stall_cycles == 0))
{
if (serviced_exe)
{

8
simX/enc.cpp
View file

@ -289,8 +289,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
trace_inst->vd = ((code>>shift_rd) & reg_mask);
//trace_inst->vs2 = ((code>>shift_rs2) & reg_mask);
break;
case Opcode::VS:
@ -304,8 +304,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
trace_inst->rd = ((code>>shift_rd) & reg_mask);
trace_inst->rs2 = ((code>>shift_rs2) & reg_mask);
//trace_inst->vd = ((code>>shift_rd) & reg_mask);
trace_inst->vs1 = ((code>>shift_rd) & reg_mask); //vs3
break;
}
break;

1
simX/include/core.h
View file

@ -107,6 +107,7 @@ namespace Harp {
VerilatedVcdC * m_trace;
bool renameTable[32][32];
bool vecRenameTable[32];
bool stallWarp[32];
bool foundSchedule;

5
simX/include/trace.h
View file

@ -17,6 +17,11 @@ namespace Harp {
int rs2;
int rd;
//Encoder
int vs1;
int vs2;
int vd;
// Instruction execute
bool is_lw;
bool is_sw;

25
simX/instruction.cpp
View file

@ -3,6 +3,7 @@
*******************************************************************************/
#include <iostream>
#include <stdlib.h>
#include <math.h>
#include "include/instruction.h"
#include "include/obj.h"
@ -1092,7 +1093,9 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
is_vec = true;
switch(func3) {
case 0: // vector-vector
trace_inst->vs1 = rsrc[0];
trace_inst->vs2 = rsrc[1];
trace_inst->vd = rdest;
switch(func6)
{
case 0:
@ -1507,6 +1510,9 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
case 2:
{
trace_inst->vs1 = rsrc[0];
trace_inst->vs2 = rsrc[1];
trace_inst->vd = rdest;
Word VLMAX = (c.vtype.vlmul * c.VLEN)/c.vtype.vsew;
switch(func6){
@ -2012,13 +2018,18 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
c.vtype.vediv = vediv;
c.vtype.vsew = vsew;
c.vtype.vlmul = vlmul;
D(3, "lmul:" << vlmul << " sew:" << vsew << " ediv: " << vediv);
Word VLMAX = (vlmul * c.VLEN)/vsew;
D(3, "lmul:" << vlmul << " sew:" << vsew << " ediv: " << vediv << "rsrc" << reg[rsrc[0]] << "VLMAX" << VLMAX);
if(reg[rsrc[0]] <= VLMAX){
c.vl = reg[rsrc[0]];
}
if(reg[rsrc[0]] >= (2*VLMAX)) {
else if(reg[rsrc[0]] < 2*VLMAX) {
c.vl = (int)ceil((reg[rsrc[0]]*1.0)/2.0);
cout << "Length:" << c.vl << ceil(reg[rsrc[0]]/2) << endl;
}
else if(reg[rsrc[0]] >= (2*VLMAX)) {
c.vl = VLMAX;
}
reg[rdest] = c.vl;
@ -2060,8 +2071,8 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
int * result_ptr = (int *) vd[i].val;
*result_ptr = data_read;
//trace_inst->is_lw = true;
//trace_inst->mem_addresses[t] = memAddr;
trace_inst->is_lw = true;
trace_inst->mem_addresses[i] = memAddr;
}
/*for(Word i = c.vl; i < VLMAX; i++){
int * result_ptr = (int *) vd[i].val;
@ -2099,8 +2110,8 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
std::cout << "STORE MEM ADDRESS: " << std::hex << memAddr << "\n";
//trace_inst->is_sw = true;
//trace_inst->mem_addresses[t] = memAddr;
trace_inst->is_sw = true;
trace_inst->mem_addresses[i] = memAddr;
switch (vlsWidth)
{