Fixed some simX bugs

emulator/enc.cpp

@@ -381,7 +381,15 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx) {
 
       imeed  = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
 
-      inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
+      // cout << "Immediate src: " << hex << imeed << "\n";
+      // cout << "bit 20 = " << bit_20 << '\n';
+
+      // if (bit_20 == 1)
+      // {
+      //   imeed = imeed * -1;
+      // }
+
+      inst.setSrcImm(signExt(imeed, 21, j_immed_mask));
       usedImm = true;
       break;
    defualt:

emulator/include/mem.h

@@ -53,32 +53,18 @@ namespace Harp {
   };
 
   class Core;
-  // class ConsoleMemDevice : public MemDevice {
-  // public:
-  //   ConsoleMemDevice(Size wS, std::ostream &o, Core &core, bool batch = false);
-  //   ~ConsoleMemDevice() {} 
+  class ConsoleMemDevice : public MemDevice {
+  public:
+    ConsoleMemDevice(Size wS, std::ostream &o, Core &core, bool batch = false) {}
+    ~ConsoleMemDevice() {} 
 
-  //   //virtual Size wordSize() const { return wordSize; }
-  //   virtual Size size() const { return wordSize; }
-  //   virtual Word read(Addr) { pthread_mutex_lock(&cBufLock);
-  //                             char c = cBuf.front();
-  //                             cBuf.pop();
-  //                             pthread_mutex_unlock(&cBufLock);
-  //                             return Word(c); }
-  //   virtual void write(Addr a, Word w) { output << char(w); }
+    //virtual Size wordSize() const { return wordSize; }
+    virtual Size size() const { return 1; }
+    virtual Word read(Addr) { Word(5); }
+    virtual void write(Addr a, Word w) { }
 
-  //   void poll();
-
-  //   friend void *Harp::consoleInputThread(void *);
-
-  // private:
-  //   std::ostream &output;
-  //   Size wordSize;
-  //   Core &core;
-
-  //   std::queue<char> cBuf;
-  //   pthread_mutex_t cBufLock;
-  // };
+    void poll() {}
+  };
 
   class DiskControllerMemDevice : public MemDevice {
   public:

emulator/instruction.cpp

@@ -578,9 +578,15 @@ void Instruction::executeOn(Warp &c) {
         reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4);
         break;
       case JAL_INST:
-        //std::cout << "JAL_INST\n";
+        std::cout << "JAL_INST\n";
         if (!pcSet) nextPc = (c.pc - 4) + immsrc;
-        if (!pcSet) {/*std::cout << "JAL... SETTING PC: " << nextPc << "\n"; */}
+
+        if (!pcSet)
+        {
+          std::cout << "JAL... immsrc: " << hex << immsrc << "\n";
+          std::cout << "JAL... pc base: " << hex << (c.pc - 4) << "\n";
+          std::cout << "JAL... SETTING PC: " << nextPc << "\n";
+        }
         if (rdest != 0)
         {
           reg[rdest] = c.pc;

emulator/test_riscv.sh

@@ -1,5 +1,6 @@
 echo start > results.txt
 
 # echo ../kernel/vortex_test.hex
-./harptool -E -a rv32i --core ../runtime/mains/simple/vx_simple_main.hex  -s -b 1> emulator.debug
+# ./harptool -E -a rv32i --core ../runtime/mains/simple/vx_simple_main.hex  -s -b 1> emulator.debug
+./harptool -E -a rv32i --core ../benchmarks/opencl/sgemm/sgemm.hex  -s -b 1> emulator.debug
 # ./harptool -E -a rv32i --core ../runtime/mains/vector_test/vx_vector_main.hex  -s -b 1> emulator.debug

simX/core.cpp

@@ -405,11 +405,11 @@ void Core::fetch()
     printTrace(&inst_in_fetch, "Fetch");
    
     // #ifdef PRINT_ACTIVE_THREADS
-    // for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) {
-    //   if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) cout << " 1";
-    //   else cout << " 0";
-    //   if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) cout << ',';
-    // }
+    for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) {
+      if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) cout << " 1";
+      else cout << " 0";
+      if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) cout << ',';
+    }
     // #endif
 
   
@@ -430,7 +430,7 @@ void Core::decode()
         INIT_TRACE(inst_in_fetch);
     }
 
-    printTrace(&inst_in_decode, "Decode");
+    //printTrace(&inst_in_decode, "Decode");
 }
 
 void Core::scheduler()
@@ -442,7 +442,7 @@ void Core::scheduler()
         INIT_TRACE(inst_in_decode);
     }
 
-    printTrace(&inst_in_scheduler, "scheduler");
+    //printTrace(&inst_in_scheduler, "scheduler");
 }
 
 void Core::load_store()
@@ -496,7 +496,7 @@ void Core::load_store()
 
     if (inst_in_lsu.mem_stall_cycles > 0) inst_in_lsu.mem_stall_cycles--;
 
-    printTrace(&inst_in_lsu, "LSU");
+    //printTrace(&inst_in_lsu, "LSU");
 }
 
 void Core::execute_unit()
@@ -548,7 +548,7 @@ void Core::execute_unit()
 
     // }
 
-    printTrace(&inst_in_exe, "execute_unit");
+    //printTrace(&inst_in_exe, "execute_unit");
     // INIT_TRACE(inst_in_exe);
 }
 
@@ -604,7 +604,7 @@ void Core::writeback()
 
     // if (!serviced_exe && !serviced_mem) INIT_TRACE(inst_in_wb);
 
-    printTrace(&inst_in_wb, "Writeback");
+    //printTrace(&inst_in_wb, "Writeback");
 
 }
 
@@ -712,12 +712,12 @@ void Warp::step(trace_inst_t * trace_inst) {
 
  
   // At Debug Level 3, print debug info after each instruction.
-  #ifdef USE_DEBUG
-    if (USE_DEBUG >= 3) {
+  // #ifdef USE_DEBUG
+    // if (USE_DEBUG >= 3) {
       D(3, "Register state:");
       for (unsigned i = 0; i < reg[0].size(); ++i) {
         D_RAW("  %r" << setfill(' ') << setw(2) << dec << i << ':');
-        for (unsigned j = 0; j < reg.size(); ++j) 
+        for (unsigned j = 0; j < (this->activeThreads); ++j) 
           D_RAW(' ' << setfill('0') << setw(8) << hex << reg[j][i] << setfill(' ') << ' ');
         D_RAW('(' << shadowReg[i] << ')' << endl);
       }
@@ -729,8 +729,8 @@ void Warp::step(trace_inst_t * trace_inst) {
       D_RAW(endl);
       D_RAW(endl);
       D_RAW(endl);
-    }
-  #endif
+    // }
+  // #endif
 
   // Clean up.
   delete inst;

simX/enc.cpp

@@ -208,7 +208,7 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
 
       imeed  = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
 
-      inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
+      inst.setSrcImm(signExt(imeed, 21, j_immed_mask));
       usedImm = true;
 
       trace_inst->valid_inst = true;

simX/test_riscv.sh

@@ -3,4 +3,4 @@ echo start > results.txt
 # echo ../kernel/vortex_test.hex
 make
 printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
-cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/fares/Desktop/Vortex/rvvector/basic/vx_vector_main.hex  -s -b 1> emulator.debug
+cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/fares/Desktop/Vortex/runtime/mains/simple/vx_simple_main.hex  -s -b 1> emulator.debug