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block ram refactoring (multi-porting supporting and simulation support)

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This commit is contained in:
Blaise Tine 2021-08-26 08:19:44 -07:00
parent 06a6857508
commit d91d56d126
14 changed files with 480 additions and 353 deletions
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37
hw/rtl/VX_gpr_ram_f.v
View file

@ -1,37 +0,0 @@
`include "VX_define.vh"
`TRACING_OFF
module VX_gpr_ram_f #(
parameter DATAW = 1,
parameter DEPTH = 1,
parameter ADDRW = $clog2(DEPTH)
) (
input wire clk,
input wire wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [ADDRW-1:0] raddr1,
input wire [ADDRW-1:0] raddr2,
input wire [ADDRW-1:0] raddr3,
output wire [DATAW-1:0] rdata1,
output wire [DATAW-1:0] rdata2,
output wire [DATAW-1:0] rdata3
);
reg [DATAW-1:0] mem [DEPTH-1:0];
initial mem = '{default: 0};
always @(posedge clk) begin
if (wren) begin
mem [waddr] <= wdata;
end
end
assign rdata1 = mem [raddr1];
assign rdata2 = mem [raddr2];
assign rdata3 = mem [raddr3];
endmodule
`TRACING_ON

34
hw/rtl/VX_gpr_ram_i.v
View file

@ -1,34 +0,0 @@
`include "VX_define.vh"
`TRACING_OFF
module VX_gpr_ram_i #(
parameter DATAW = 1,
parameter DEPTH = 1,
parameter ADDRW = $clog2(DEPTH)
) (
input wire clk,
input wire wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [ADDRW-1:0] raddr1,
input wire [ADDRW-1:0] raddr2,
output wire [DATAW-1:0] rdata1,
output wire [DATAW-1:0] rdata2
);
reg [DATAW-1:0] mem [DEPTH-1:0];
initial mem = '{default: 0};
always @(posedge clk) begin
if (wren) begin
mem [waddr] <= wdata;
end
end
assign rdata1 = mem [raddr1];
assign rdata2 = mem [raddr2];
endmodule
`TRACING_ON

62
hw/rtl/VX_gpr_stage.v
View file

@ -21,9 +21,9 @@ module VX_gpr_stage #(
wire write_enable = writeback_if.valid && (writeback_if.rd != 0);
`ifdef EXT_F_ENABLE
localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS;
localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2, rdata3;
wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2, raddr3;
wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2, raddr3;
assign waddr = {writeback_if.wid, writeback_if.rd};
assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
@ -31,20 +31,20 @@ module VX_gpr_stage #(
assign raddr3 = {gpr_req_if.wid, gpr_req_if.rs3};
for (genvar i = 0; i < `NUM_THREADS; i++) begin
VX_gpr_ram_f #(
.DATAW (32),
.DEPTH (RAM_DEPTH)
) gpr_ram_f (
.clk (clk),
.wren (write_enable && writeback_if.tmask[i]),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.raddr1 (raddr1),
.raddr2 (raddr2),
.raddr3 (raddr3),
.rdata1 (rdata1[i]),
.rdata2 (rdata2[i]),
.rdata3 (rdata3[i])
VX_dp_ram #(
.RD_PORTS (3),
.DATAW (32),
.SIZE (RAM_SIZE),
.INIT_ENABLE (1),
.INIT_VALUE (0)
) dp_ram (
.clk (clk),
.wren (write_enable && writeback_if.tmask[i]),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.rden (3'b111),
.raddr ({raddr3, raddr2, raddr1}),
.rdata ({rdata3[i], rdata2[i], rdata1[i]})
);
end
@ -52,9 +52,9 @@ module VX_gpr_stage #(
assign gpr_rsp_if.rs2_data = rdata2;
assign gpr_rsp_if.rs3_data = rdata3;
`else
localparam RAM_DEPTH = `NUM_WARPS * `NUM_REGS;
localparam RAM_SIZE = `NUM_WARPS * `NUM_REGS;
wire [`NUM_THREADS-1:0][31:0] rdata1, rdata2;
wire [$clog2(RAM_DEPTH)-1:0] waddr, raddr1, raddr2;
wire [$clog2(RAM_SIZE)-1:0] waddr, raddr1, raddr2;
assign waddr = {writeback_if.wid, writeback_if.rd};
assign raddr1 = {gpr_req_if.wid, gpr_req_if.rs1};
@ -62,18 +62,20 @@ module VX_gpr_stage #(
`UNUSED_VAR (gpr_req_if.rs3)
for (genvar i = 0; i < `NUM_THREADS; i++) begin
VX_gpr_ram_i #(
.DATAW (32),
.DEPTH (RAM_DEPTH)
) gpr_ram_i (
.clk (clk),
.wren (write_enable && writeback_if.tmask[i]),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.raddr1 (raddr1),
.raddr2 (raddr2),
.rdata1 (rdata1[i]),
.rdata2 (rdata2[i])
VX_dp_ram #(
.RD_PORTS (2),
.DATAW (32),
.SIZE (RAM_SIZE),
.INIT_ENABLE (1),
.INIT_VALUE (0)
) dp_ram (
.clk (clk),
.wren (write_enable && writeback_if.tmask[i]),
.waddr (waddr),
.wdata (writeback_if.data[i]),
.rden (2'b11),
.raddr ({raddr2, raddr1}),
.rdata ({rdata2[i], rdata1[i]})
);
end

19
hw/rtl/VX_icache_stage.v
View file

@ -33,16 +33,17 @@ module VX_icache_stage #(
wire [`NUM_THREADS-1:0] rsp_tmask;
VX_dp_ram #(
.DATAW(32 + `NUM_THREADS),
.SIZE(`NUM_WARPS),
.FASTRAM(1)
.DATAW (32 + `NUM_THREADS),
.SIZE (`NUM_WARPS),
.LUTRAM (1)
) req_metadata (
.clk(clk),
.waddr(req_tag),
.raddr(rsp_tag),
.wren(icache_req_fire),
.din({ifetch_req_if.PC, ifetch_req_if.tmask}),
.dout({rsp_PC, rsp_tmask})
.clk (clk),
.wren (icache_req_fire),
.waddr (req_tag),
.wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}),
.rden (1'b1),
.raddr (rsp_tag),
.rdata ({rsp_PC, rsp_tmask})
);
`RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR),

20
hw/rtl/VX_ipdom_stack.v
View file

@ -38,17 +38,17 @@ module VX_ipdom_stack #(
end
VX_dp_ram #(
.DATAW(WIDTH * 2),
.SIZE(DEPTH),
.RWCHECK(1),
.FASTRAM(1)
.DATAW (WIDTH * 2),
.SIZE (DEPTH),
.LUTRAM (1)
) store (
.clk(clk),
.waddr(wr_ptr),
.raddr(rd_ptr),
.wren(push),
.din({q2, q1}),
.dout({d2, d1})
.clk (clk),
.wren (push),
.waddr (wr_ptr),
.wdata ({q2, q1}),
.rden (1'b1),
.raddr (rd_ptr),
.rdata ({d2, d1})
);
always @(posedge clk) begin

14
hw/rtl/cache/VX_data_access.v vendored
View file

@ -65,14 +65,14 @@ module VX_data_access #(
VX_sp_ram #(
.DATAW (CACHE_LINE_SIZE * 8),
.SIZE (`LINES_PER_BANK),
.BYTEENW (BYTEENW),
.RWCHECK (1)
.BYTEENW (BYTEENW)
) data_store (
.clk(clk),
.addr(line_addr),
.wren({BYTEENW{writeen}} & byte_enable),
.din(wdata),
.dout(rdata)
.clk (clk),
.addr (line_addr),
.wren ({BYTEENW{writeen}} & byte_enable),
.wdata (wdata),
.rden (1'b1),
.rdata (rdata)
);
`UNUSED_VAR (stall)

20
hw/rtl/cache/VX_miss_resrv.v vendored
View file

@ -169,17 +169,17 @@ module VX_miss_resrv #(
`LINE_TO_BYTE_ADDR(addr_table[fill_id], BANK_ID), fill_id))
VX_dp_ram #(
.DATAW (`MSHR_DATA_WIDTH),
.SIZE (MSHR_SIZE),
.RWCHECK (1),
.FASTRAM (1)
.DATAW (`MSHR_DATA_WIDTH),
.SIZE (MSHR_SIZE),
.LUTRAM (1)
) entries (
.clk (clk),
.waddr (allocate_id_r),
.raddr (dequeue_id_r),
.wren (allocate_valid),
.din (allocate_data),
.dout (dequeue_data)
.clk (clk),
.waddr (allocate_id_r),
.raddr (dequeue_id_r),
.wren (allocate_valid),
.wdata (allocate_data),
.rden (1'b1),
.rdata (dequeue_data)
);
assign allocate_ready = allocate_rdy_r;

32
hw/rtl/cache/VX_shared_mem.v vendored
View file

@ -173,14 +173,14 @@ module VX_shared_mem #(
VX_sp_ram #(
.DATAW (`WORD_WIDTH),
.SIZE (`LINES_PER_BANK),
.BYTEENW (WORD_SIZE),
.RWCHECK (1)
.BYTEENW (WORD_SIZE)
) data_store (
.clk (clk),
.addr (per_bank_core_req_addr[i]),
.wren ({WORD_SIZE{wren}} & per_bank_core_req_byteen[i]),
.din (per_bank_core_req_data[i]),
.dout (per_bank_core_rsp_data[i])
.clk (clk),
.addr (per_bank_core_req_addr[i]),
.wren ({WORD_SIZE{wren}} & per_bank_core_req_byteen[i]),
.wdata (per_bank_core_req_data[i]),
.rden (1'b1),
.rdata (per_bank_core_rsp_data[i])
);
end
@ -216,18 +216,19 @@ module VX_shared_mem #(
reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in;
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in;
always @(*) begin
core_rsp_valids_in = 0;
core_rsp_data_in = 'x;
core_rsp_tag_in = 'x;
bank_rsp_sel_cur = 0;
always @(*) begin
core_rsp_tag_in = 'x;
for (integer i = NUM_BANKS-1; i >= 0; --i) begin
if (per_bank_req_reads[i] && ~bank_rsp_sel_prv[i]) begin
core_rsp_tag_in = per_bank_core_req_tag[i];
end
end
end
always @(*) begin
core_rsp_valids_in = 0;
core_rsp_data_in = 'x;
bank_rsp_sel_cur = 0;
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_req_valid[i]
&& (core_rsp_tag_in[CORE_TAG_ID_BITS-1:0] == per_bank_core_req_tag[i][CORE_TAG_ID_BITS-1:0])) begin
@ -278,13 +279,16 @@ module VX_shared_mem #(
reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel;
`IGNORE_UNUSED_END
always @(*) begin
always @(*) begin
core_req_tag_sel ='x;
for (integer i = NUM_BANKS-1; i >= 0; --i) begin
if (per_bank_core_req_valid[i]) begin
core_req_tag_sel = per_bank_core_req_tag[i];
end
end
end
always @(*) begin
is_multi_tag_req = 0;
for (integer i = 0; i < NUM_BANKS; ++i) begin
if (per_bank_core_req_valid[i]

15
hw/rtl/cache/VX_tag_access.v vendored
View file

@ -48,14 +48,15 @@ module VX_tag_access #(
VX_sp_ram #(
.DATAW(`TAG_SELECT_BITS + 1),
.SIZE(`LINES_PER_BANK),
.INITZERO(1),
.RWCHECK(1)
.INIT_ENABLE(1),
.INIT_VALUE(0)
) tag_store (
.clk(clk),
.addr(line_addr),
.wren(fill),
.din({!is_flush, line_tag}),
.dout({read_valid, read_tag})
.clk( clk),
.addr (line_addr),
.wren (fill),
.wdata ({!is_flush, line_tag}),
.rden (1'b1),
.rdata ({read_valid, read_tag})
);
assign tag_match = read_valid && (line_tag == read_tag);

274
hw/rtl/libs/VX_dp_ram.v
View file

@ -2,178 +2,286 @@
`TRACING_OFF
module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter RD_PORTS = 1,
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
input wire clk,
input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata,
input wire [RD_PORTS-1:0] rden,
input wire [RD_PORTS-1:0][ADDRW-1:0] raddr,
output wire [RD_PORTS-1:0][DATAW-1:0] rdata
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
`STATIC_ASSERT(!LUTRAM || (RD_PORTS == 1), ("multi-porting not supported on LUTRAM"))
if (FASTRAM) begin
`define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[raddr];
if (rden)
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
dout_r <= mem[raddr];
ram[waddr] <= wdata;
if (rden)
rdata_r <= ram[raddr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
assign rdata = ram[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
assign dout = mem[raddr];
assign rdata = ram[raddr];
end
end
end else begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
dout_r <= mem[raddr];
ram[waddr] <= wdata;
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
if (RWCHECK) begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
assign dout = mem[raddr];
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
ram[waddr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[raddr];
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[waddr] <= din;
ram[waddr] <= wdata;
end
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
assign dout = mem[raddr];
end
end
end
end
`else
if (OUTPUT_REG) begin
reg [RD_PORTS-1:0][DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
for (integer i = 0; i < RD_PORTS; ++i) begin
if (rden[i])
rdata_r[i] <= ram[raddr[i]];
end
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
prev_write <= wren;
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_waddr)
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = ram[raddr[i]];
end
end else begin
for (genvar i = 0; i < RD_PORTS; ++i) begin
assign rdata[i] = (prev_write && (prev_waddr == raddr[i])) ? prev_data : ram[raddr[i]];
end
end
end
end
`endif
endmodule
`TRACING_ON

4
hw/rtl/libs/VX_elastic_buffer.v
View file

@ -5,7 +5,7 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter FASTRAM = 0
parameter LUTRAM = 0
) (
input wire clk,
input wire reset,
@ -56,7 +56,7 @@ module VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) queue (
.clk (clk),
.reset (reset),

32
hw/rtl/libs/VX_fifo_queue.v
View file

@ -9,7 +9,7 @@ module VX_fifo_queue #(
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0,
parameter FASTRAM = 1
parameter LUTRAM = 1
) (
input wire clk,
input wire reset,
@ -157,15 +157,15 @@ module VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
.raddr(rd_ptr_r),
.wren(push),
.din(data_in),
.dout(data_out)
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_r),
.rdata (data_out)
);
end else begin
@ -200,15 +200,15 @@ module VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.din(data_in),
.dout(dout)
.clk (clk),
.wren (push),
.waddr (wr_ptr_r),
.wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_n_r),
.rdata (dout)
);
always @(posedge clk) begin

28
hw/rtl/libs/VX_index_buffer.v
View file

@ -2,10 +2,10 @@
`TRACING_OFF
module VX_index_buffer #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter FASTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
parameter DATAW = 1,
parameter SIZE = 1,
parameter LUTRAM = 1,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
@ -68,17 +68,17 @@ module VX_index_buffer #(
end
VX_dp_ram #(
.DATAW(DATAW),
.SIZE(SIZE),
.RWCHECK(1),
.FASTRAM(FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.LUTRAM (LUTRAM)
) data_table (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.din(write_data),
.dout(read_data)
.clk (clk),
.wren (acquire_slot),
.waddr (write_addr),
.wdata (write_data),
.rden (1'b1),
.raddr (read_addr),
.rdata (read_data)
);
assign write_addr = write_addr_r;

242
hw/rtl/libs/VX_sp_ram.v
View file

@ -2,177 +2,259 @@
`TRACING_OFF
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
input wire [DATAW-1:0] wdata,
input wire rden,
output wire [DATAW-1:0] rdata
);
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
`define RAM_INITIALIZATION \
if (INIT_ENABLE) begin \
if (INIT_FILE != "") begin \
initial $readmemh(INIT_FILE, ram); \
end else begin \
initial ram = '{default: INIT_VALUE}; \
end \
end
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[addr];
if (rden)
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
dout_r <= mem[addr];
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end
end else begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
dout_r <= mem[addr];
if (rden)
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
dout_r <= mem[addr];
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign dout = dout_r;
assign rdata = rdata_r;
end else begin
if (RWCHECK) begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end else begin
if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
ram[addr][i] <= wdata[i * 8 +: 8];
end
end
assign dout = mem[addr];
assign rdata = ram[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
reg [DATAW-1:0] ram [SIZE-1:0];
if (INITZERO) begin
initial mem = '{default: 0};
end
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
mem[addr] <= din;
ram[addr] <= wdata;
end
assign dout = mem[addr];
assign rdata = ram[addr];
end
end
end
end
`else
if (OUTPUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
if (rden)
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
if (rden)
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8];
end
prev_write <= (| wren);
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_addr;
reg prev_write;
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
prev_write <= wren;
prev_data <= ram[addr];
prev_addr <= addr;
end
if (LUTRAM || !NO_RWCHECK) begin
`UNUSED_VAR (prev_write)
`UNUSED_VAR (prev_data)
`UNUSED_VAR (prev_addr)
assign rdata = ram[addr];
end else begin
assign rdata = (prev_write && (prev_addr == addr)) ? prev_data : ram[addr];
end
end
end
`endif
endmodule
`TRACING_ON