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More 64b fixes in ALU, Verilator exit code and ISA tests

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Shashank Holla 2023-03-16 02:43:39 -04:00 • committed by Blaise Tine
parent bb539a25f8
commit d98643076d
2 changed files with 6 additions and 1 deletions
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5
hw/rtl/VX_trace_info.vh
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@ -59,6 +59,11 @@
`INST_ALU_AND: `TRACE(level, ("AND")); \
`INST_ALU_LUI: `TRACE(level, ("LUI")); \
`INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); \
`INST_ALU_ADD_W: `TRACE(level, ("ADD_W")); \
`INST_ALU_SUB_W: `TRACE(level, ("SUB_W")); \
`INST_ALU_SLL_W: `TRACE(level, ("SLL_W")); \
`INST_ALU_SRL_W: `TRACE(level, ("SRL_W")); \
`INST_ALU_SRA_W: `TRACE(level, ("SRA_W")); \
default: `TRACE(level, ("?")); \
endcase \
end \

2
hw/rtl/Vortex.sv
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@ -116,7 +116,7 @@ module Vortex (
`endif
wire sim_ebreak /* verilator public */;
wire [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value /* verilator public */;
wire [`NUM_REGS-1:0][31:0] sim_wb_value /* verilator public */;
wire [`NUM_CLUSTERS-1:0] per_cluster_sim_ebreak;
wire [`NUM_CLUSTERS-1:0][`NUM_REGS-1:0][`XLEN-1:0] per_cluster_sim_wb_value;
assign sim_ebreak = per_cluster_sim_ebreak[0];