mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor single-thread fix
This commit is contained in:
Blaise Tine
parent
0cd2ea458f
commit
daf1360d83
4 changed files with 64 additions and 64 deletions
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -28,17 +28,17 @@ struct params_t {
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uint32_t words_per_line;
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uint32_t log2_num_inputs;
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uint32_t word_select_addr_start;
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uint32_t word_select_addr_end;
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int32_t word_select_addr_start;
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int32_t word_select_addr_end;
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uint32_t bank_select_addr_start;
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uint32_t bank_select_addr_end;
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int32_t bank_select_addr_start;
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int32_t bank_select_addr_end;
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uint32_t set_select_addr_start;
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uint32_t set_select_addr_end;
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int32_t set_select_addr_start;
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int32_t set_select_addr_end;
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uint32_t tag_select_addr_start;
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uint32_t tag_select_addr_end;
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int32_t tag_select_addr_start;
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int32_t tag_select_addr_end;
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params_t(const CacheSim::Config& config) {
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int32_t offset_bits = config.L - config.W;
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@ -53,7 +53,7 @@ struct params_t {
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this->words_per_line = 1 << offset_bits;
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assert(config.ports_per_bank <= this->words_per_line);
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// Word select
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this->word_select_addr_start = config.W;
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this->word_select_addr_end = (this->word_select_addr_start+offset_bits-1);
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@ -91,7 +91,7 @@ struct params_t {
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else
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return 0;
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}
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uint64_t mem_addr(uint32_t bank_id, uint32_t set_id, uint64_t tag) const {
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uint64_t addr(0);
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if (bank_select_addr_end >= bank_select_addr_start)
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@ -119,8 +119,8 @@ struct line_t {
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struct set_t {
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std::vector<line_t> lines;
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set_t(uint32_t num_ways)
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: lines(num_ways)
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set_t(uint32_t num_ways)
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: lines(num_ways)
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{}
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void clear() {
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@ -136,7 +136,7 @@ struct bank_req_port_t {
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bool valid;
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void clear() {
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valid = false;
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valid = false;
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}
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};
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@ -158,7 +158,7 @@ struct bank_req_t {
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bool write;
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bank_req_t(uint32_t num_ports)
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: ports(num_ports)
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: ports(num_ports)
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{}
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void clear() {
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@ -173,8 +173,8 @@ struct mshr_entry_t {
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bank_req_t bank_req;
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uint32_t line_id;
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mshr_entry_t(uint32_t num_ports)
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: bank_req(num_ports)
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mshr_entry_t(uint32_t num_ports)
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: bank_req(num_ports)
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{}
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void clear() {
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@ -190,13 +190,13 @@ private:
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public:
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MSHR(uint32_t size, uint32_t num_ports)
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: entries_(size, num_ports)
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, size_(0)
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, size_(0)
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{}
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bool empty() const {
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return (0 == size_);
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}
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bool full() const {
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return (size_ == entries_.size());
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}
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@ -204,7 +204,7 @@ public:
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bool lookup(const bank_req_t& bank_req) {
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for (auto& entry : entries_) {;
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if (entry.bank_req.type != bank_req_t::None
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&& entry.bank_req.set_id == bank_req.set_id
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&& entry.bank_req.set_id == bank_req.set_id
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&& entry.bank_req.tag == bank_req.tag) {
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return true;
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}
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@ -230,8 +230,8 @@ public:
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assert(root_entry.bank_req.type == bank_req_t::Core);
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// mark all related mshr entries for replay
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for (auto& entry : entries_) {
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if (entry.bank_req.type == bank_req_t::Core
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&& entry.bank_req.set_id == root_entry.bank_req.set_id
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if (entry.bank_req.type == bank_req_t::Core
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&& entry.bank_req.set_id == root_entry.bank_req.set_id
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&& entry.bank_req.tag == root_entry.bank_req.tag) {
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entry.bank_req.type = bank_req_t::Replay;
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}
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@ -263,8 +263,8 @@ struct bank_t {
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std::vector<set_t> sets;
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MSHR mshr;
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bank_t(const CacheSim::Config& config,
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const params_t& params)
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bank_t(const CacheSim::Config& config,
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const params_t& params)
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: sets(params.sets_per_bank, params.lines_per_set)
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, mshr(config.mshr_size, config.ports_per_bank)
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{}
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@ -297,7 +297,7 @@ private:
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uint64_t pending_fill_reqs_;
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public:
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Impl(CacheSim* simobject, const Config& config)
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Impl(CacheSim* simobject, const Config& config)
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: simobject_(simobject)
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, config_(config)
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, params_(config)
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@ -319,7 +319,7 @@ public:
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simobject->MemRspPort.bind(&bypass_switch_->RspOut.at(0));
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return;
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}
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bypass_switch_ = MemSwitch::Create(sname, ArbiterType::Priority, 2);
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bypass_switch_->ReqOut.at(0).bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&bypass_switch_->RspOut.at(0));
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@ -480,7 +480,7 @@ public:
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// process active request
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this->processBankRequests();
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}
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}
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const PerfStats& perf_stats() const {
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return perf_stats_;
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@ -517,7 +517,7 @@ private:
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for (uint32_t bank_id = 0, n = (1 << config_.B); bank_id < n; ++bank_id) {
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auto& bank = banks_.at(bank_id);
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auto pipeline_req = pipeline_reqs_.at(bank_id);
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switch (pipeline_req.type) {
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case bank_req_t::None:
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break;
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@ -559,7 +559,7 @@ private:
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repl_line_id = i;
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}
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if (line.valid) {
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if (line.tag == pipeline_req.tag) {
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if (line.tag == pipeline_req.tag) {
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hit_line_id = i;
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line.lru_ctr = 0;
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} else {
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@ -647,7 +647,7 @@ private:
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// allocate MSHR
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auto mshr_id = bank.mshr.allocate(pipeline_req, (free_line_id != -1) ? free_line_id : repl_line_id);
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// send fill request
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if (!mshr_pending) {
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MemReq mem_req;
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@ -672,7 +672,7 @@ private:
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///////////////////////////////////////////////////////////////////////////////
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CacheSim::CacheSim(const SimContext& ctx, const char* name, const Config& config)
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CacheSim::CacheSim(const SimContext& ctx, const char* name, const Config& config)
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: SimObject<CacheSim>(ctx, name)
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, CoreReqPorts(config.num_inputs, this)
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, CoreRspPorts(config.num_inputs, this)
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -25,10 +25,10 @@
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using namespace vortex;
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Core::Core(const SimContext& ctx,
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uint32_t core_id,
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Core::Core(const SimContext& ctx,
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uint32_t core_id,
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Socket* socket,
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const Arch &arch,
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const Arch &arch,
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const DCRS &dcrs)
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: SimObject(ctx, "core")
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, icache_req_ports(1, this)
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@ -67,7 +67,7 @@ Core::Core(const SimContext& ctx,
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(1 << LMEM_LOG_SIZE),
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LSU_WORD_SIZE,
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LSU_NUM_REQS,
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LMEM_NUM_BANKS,
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log2ceil(LMEM_NUM_BANKS),
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false
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});
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@ -82,21 +82,21 @@ Core::Core(const SimContext& ctx,
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for (uint32_t c = 0; c < DCACHE_CHANNELS; ++c) {
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uint32_t i = b * DCACHE_CHANNELS + c;
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mem_coalescers_.at(b)->ReqOut.at(c).bind(&dcache_req_ports.at(i));
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dcache_rsp_ports.at(i).bind(&mem_coalescers_.at(b)->RspOut.at(c));
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dcache_rsp_ports.at(i).bind(&mem_coalescers_.at(b)->RspOut.at(c));
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}
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}
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// connect lsu demux
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for (uint32_t b = 0; b < NUM_LSU_BLOCKS; ++b) {
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for (uint32_t c = 0; c < LSU_CHANNELS; ++c) {
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uint32_t i = b * LSU_CHANNELS + c;
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auto lmem_demux = lsu_demux_.at(i);
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lmem_demux->ReqDC.bind(&mem_coalescers_.at(b)->ReqIn.at(c));
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mem_coalescers_.at(b)->RspIn.at(c).bind(&lmem_demux->RspDC);
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lmem_demux->ReqSM.bind(&local_mem_->Inputs.at(i));
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local_mem_->Outputs.at(i).bind(&lmem_demux->RspSM);
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local_mem_->Outputs.at(i).bind(&lmem_demux->RspSM);
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}
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}
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@ -136,7 +136,7 @@ void Core::reset() {
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for (auto& exe_unit : func_units_) {
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exe_unit->reset();
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}
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for (auto& commit_arb : commit_arbs_) {
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commit_arb->reset();
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}
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@ -243,13 +243,13 @@ void Core::decode() {
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DT(3, "pipeline-decode: " << *trace);
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// insert to ibuffer
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// insert to ibuffer
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ibuffer.push(trace);
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decode_latch_.pop();
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}
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void Core::issue() {
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void Core::issue() {
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// operands to dispatchers
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& operand = operands_.at(i);
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@ -348,7 +348,7 @@ void Core::execute() {
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}
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void Core::commit() {
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// process completed instructions
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// process completed instructions
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for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
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auto& commit_arb = commit_arbs_.at(i);
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if (commit_arb->Outputs.at(0).empty())
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -24,8 +24,8 @@ protected:
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LocalMem* simobject_;
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Config config_;
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RAM ram_;
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uint32_t bank_sel_addr_start_;
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uint32_t bank_sel_addr_end_;
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int32_t bank_sel_addr_start_;
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int32_t bank_sel_addr_end_;
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PerfStats perf_stats_;
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uint64_t to_local_addr(uint64_t addr) {
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@ -36,14 +36,14 @@ protected:
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}
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public:
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Impl(LocalMem* simobject, const Config& config)
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Impl(LocalMem* simobject, const Config& config)
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: simobject_(simobject)
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, config_(config)
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, ram_(config.capacity)
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, bank_sel_addr_start_(0)
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, bank_sel_addr_end_(0 + log2ceil(config.num_banks)-1)
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, bank_sel_addr_end_(config.B-1)
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{}
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virtual ~Impl() {}
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void reset() {
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@ -63,7 +63,7 @@ public:
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}
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void tick() {
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std::vector<bool> in_used_banks(config_.num_banks);
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std::vector<bool> in_used_banks(1 << config_.B);
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for (uint32_t req_id = 0; req_id < config_.num_reqs; ++req_id) {
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auto& core_req_port = simobject_->Inputs.at(req_id);
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if (core_req_port.empty())
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@ -72,7 +72,7 @@ public:
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auto& core_req = core_req_port.front();
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uint32_t bank_id = 0;
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if (bank_sel_addr_start_ <= bank_sel_addr_end_) {
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if (bank_sel_addr_end_ >= bank_sel_addr_start_) {
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bank_id = (uint32_t)bit_getw(core_req.addr, bank_sel_addr_start_, bank_sel_addr_end_);
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}
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@ -99,15 +99,15 @@ public:
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}
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}
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const PerfStats& perf_stats() const {
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return perf_stats_;
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const PerfStats& perf_stats() const {
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return perf_stats_;
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}
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};
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///////////////////////////////////////////////////////////////////////////////
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LocalMem::LocalMem(const SimContext& ctx, const char* name, const Config& config)
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: SimObject<LocalMem>(ctx, name)
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LocalMem::LocalMem(const SimContext& ctx, const char* name, const Config& config)
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: SimObject<LocalMem>(ctx, name)
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, Inputs(config.num_reqs, this)
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, Outputs(config.num_reqs, this)
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, impl_(new Impl(this, config))
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
|
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// You may obtain a copy of the License at
|
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// http://www.apache.org/licenses/LICENSE-2.0
|
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
|
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -24,7 +24,7 @@ public:
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uint32_t capacity;
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uint32_t line_size;
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uint32_t num_reqs;
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uint32_t num_banks;
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uint32_t B; // log2 number of banks
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bool write_reponse;
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};
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@ -33,7 +33,7 @@ public:
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uint64_t writes;
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uint64_t bank_stalls;
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PerfStats()
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PerfStats()
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: reads(0)
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, writes(0)
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, bank_stalls(0)
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@ -50,7 +50,7 @@ public:
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std::vector<SimPort<MemReq>> Inputs;
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std::vector<SimPort<MemRsp>> Outputs;
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LocalMem(const SimContext& ctx, const char* name, const Config& config);
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LocalMem(const SimContext& ctx, const char* name, const Config& config);
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virtual ~LocalMem();
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void reset();
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