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runtime API refactoring to support memory reservation and protection

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This commit is contained in:
Blaise Tine 2024-04-28 04:23:00 -07:00
parent c554f53e44
commit db0f0fd353
35 changed files with 3190 additions and 2081 deletions
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18
sim/rtlsim/main.cpp
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@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -61,8 +61,8 @@ static void parse_args(int argc, char **argv) {
int main(int argc, char **argv) {
int exitcode = 0;
parse_args(argc, argv);
parse_args(argc, argv);
// create memory module
vortex::RAM ram(0, RAM_PAGE_SIZE);
@ -75,14 +75,14 @@ int main(int argc, char **argv) {
// setup base DCRs
const uint64_t startup_addr(STARTUP_ADDR);
processor.write_dcr(VX_DCR_BASE_STARTUP_ADDR0, startup_addr & 0xffffffff);
processor.dcr_write(VX_DCR_BASE_STARTUP_ADDR0, startup_addr & 0xffffffff);
#if (XLEN == 64)
processor.write_dcr(VX_DCR_BASE_STARTUP_ADDR1, startup_addr >> 32);
processor.dcr_write(VX_DCR_BASE_STARTUP_ADDR1, startup_addr >> 32);
#endif
processor.write_dcr(VX_DCR_BASE_MPM_CLASS, 0);
processor.dcr_write(VX_DCR_BASE_MPM_CLASS, 0);
// load program
{
{
std::string program_ext(fileExtension(program));
if (program_ext == "bin") {
ram.loadBinImage(program, startup_addr);
@ -96,7 +96,7 @@ int main(int argc, char **argv) {
// run simulation
exitcode = processor.run();
if (riscv_test) {
if (1 == exitcode) {
std::cout << "Passed" << std::endl;