mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 22:07:41 -04:00
runtime API refactoring to support memory reservation and protection
This commit is contained in:
Blaise Tine
parent
c554f53e44
commit
db0f0fd353
35 changed files with 3190 additions and 2081 deletions
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -37,7 +37,7 @@
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#include <list>
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#include <queue>
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#include <vector>
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#include <sstream>
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#include <sstream>
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#include <unordered_map>
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#define RAMULATOR
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@ -84,7 +84,7 @@ using namespace vortex;
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static uint64_t timestamp = 0;
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double sc_time_stamp() {
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double sc_time_stamp() {
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return timestamp;
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}
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@ -95,7 +95,7 @@ static uint64_t trace_start_time = TRACE_START_TIME;
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static uint64_t trace_stop_time = TRACE_STOP_TIME;
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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@ -110,7 +110,7 @@ void sim_trace_enable(bool enable) {
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class Processor::Impl {
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public:
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Impl() {
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// force random values for unitialized signals
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// force random values for unitialized signals
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Verilated::randReset(VERILATOR_RESET_VALUE);
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Verilated::randSeed(50);
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@ -132,7 +132,7 @@ public:
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#endif
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ram_ = nullptr;
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// initialize dram simulator
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ramulator::Config ram_config;
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ram_config.add("standard", "DDR4");
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@ -147,7 +147,7 @@ public:
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// reset the device
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this->reset();
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// Turn on assertion after reset
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Verilated::assertOn(true);
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}
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@ -159,9 +159,9 @@ public:
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trace_->close();
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delete trace_;
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#endif
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delete device_;
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if (dram_) {
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dram_->finish();
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Stats::statlist.printall();
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@ -202,11 +202,11 @@ public:
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while (device_->busy) {
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if (get_ebreak()) {
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exitcode = (int)get_last_wb_value(3);
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break;
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break;
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}
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this->tick();
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}
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// reset device
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this->reset();
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@ -215,7 +215,7 @@ public:
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return exitcode;
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}
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void write_dcr(uint32_t addr, uint32_t value) {
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void dcr_write(uint32_t addr, uint32_t value) {
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device_->dcr_wr_valid = 1;
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device_->dcr_wr_addr = addr;
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device_->dcr_wr_data = value;
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@ -232,7 +232,7 @@ private:
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print_bufs_.clear();
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pending_mem_reqs_.clear();
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mem_rd_rsp_active_ = false;
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mem_wr_rsp_active_ = false;
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@ -268,7 +268,7 @@ private:
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device_->clk = 1;
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this->eval();
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#ifdef AXI_BUS
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this->eval_axi_bus(1);
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#else
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@ -276,13 +276,13 @@ private:
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#endif
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this->eval_dcr_bus(1);
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if (MEM_CYCLE_RATIO > 0) {
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if (MEM_CYCLE_RATIO > 0) {
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auto cycle = timestamp / 2;
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if ((cycle % MEM_CYCLE_RATIO) == 0)
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dram_->tick();
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} else {
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for (int i = MEM_CYCLE_RATIO; i <= 0; ++i)
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dram_->tick();
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dram_->tick();
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}
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if (!dram_queue_.empty()) {
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@ -309,14 +309,14 @@ private:
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#ifdef AXI_BUS
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void reset_axi_bus() {
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void reset_axi_bus() {
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device_->m_axi_wready[0] = 0;
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device_->m_axi_awready[0] = 0;
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device_->m_axi_arready[0] = 0;
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device_->m_axi_arready[0] = 0;
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device_->m_axi_rvalid[0] = 0;
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device_->m_axi_bvalid[0] = 0;
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}
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void eval_axi_bus(bool clk) {
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if (!clk) {
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mem_rd_rsp_ready_ = device_->m_axi_rready[0];
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@ -327,7 +327,7 @@ private:
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if (ram_ == nullptr) {
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device_->m_axi_wready[0] = 0;
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device_->m_axi_awready[0] = 0;
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device_->m_axi_arready[0] = 0;
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device_->m_axi_arready[0] = 0;
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return;
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}
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@ -335,11 +335,11 @@ private:
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if (mem_rd_rsp_active_
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&& device_->m_axi_rvalid[0] && mem_rd_rsp_ready_) {
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mem_rd_rsp_active_ = false;
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}
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if (!mem_rd_rsp_active_) {
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}
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if (!mem_rd_rsp_active_) {
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if (!pending_mem_reqs_.empty()
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&& (*pending_mem_reqs_.begin())->ready
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&& !(*pending_mem_reqs_.begin())->write) {
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&& (*pending_mem_reqs_.begin())->ready
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&& !(*pending_mem_reqs_.begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_.begin();
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auto mem_rsp = *mem_rsp_it;
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/*
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@ -348,9 +348,9 @@ private:
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printf("%02x", mem_rsp->block[(MEM_BLOCK_SIZE-1)-i]);
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}
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printf("\n");
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*/
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*/
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device_->m_axi_rvalid[0] = 1;
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device_->m_axi_rid[0] = mem_rsp->tag;
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device_->m_axi_rid[0] = mem_rsp->tag;
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device_->m_axi_rresp[0] = 0;
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device_->m_axi_rlast[0] = 1;
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memcpy(device_->m_axi_rdata[0].data(), mem_rsp->block.data(), MEM_BLOCK_SIZE);
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@ -362,46 +362,46 @@ private:
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}
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}
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// send memory write response
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// send memory write response
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if (mem_wr_rsp_active_
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&& device_->m_axi_bvalid[0] && mem_wr_rsp_ready_) {
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mem_wr_rsp_active_ = false;
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}
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if (!mem_wr_rsp_active_) {
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if (!pending_mem_reqs_.empty()
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&& (*pending_mem_reqs_.begin())->ready
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&& (*pending_mem_reqs_.begin())->ready
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&& (*pending_mem_reqs_.begin())->write) {
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auto mem_rsp_it = pending_mem_reqs_.begin();
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auto mem_rsp = *mem_rsp_it;
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/*
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printf("%0ld: [sim] MEM Wr Rsp: bank=%d, addr=%0lx\n", timestamp, last_mem_rsp_bank_, mem_rsp->addr);
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printf("%0ld: [sim] MEM Wr Rsp: bank=%d, addr=%0lx\n", timestamp, last_mem_rsp_bank_, mem_rsp->addr);
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*/
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device_->m_axi_bvalid[0] = 1;
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device_->m_axi_bvalid[0] = 1;
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device_->m_axi_bid[0] = mem_rsp->tag;
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device_->m_axi_bresp[0] = 0;
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pending_mem_reqs_.erase(mem_rsp_it);
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pending_mem_reqs_.erase(mem_rsp_it);
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mem_wr_rsp_active_ = true;
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delete mem_rsp;
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} else {
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device_->m_axi_bvalid[0] = 0;
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}
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}
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}
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// select the memory bank
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uint32_t req_addr = device_->m_axi_wvalid[0] ? device_->m_axi_awaddr[0] : device_->m_axi_araddr[0];
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// process memory requests
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if ((device_->m_axi_wvalid[0] || device_->m_axi_arvalid[0]) && running_) {
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if (device_->m_axi_wvalid[0]) {
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if (device_->m_axi_wvalid[0]) {
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uint64_t byteen = device_->m_axi_wstrb[0];
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uint64_t base_addr = device_->m_axi_awaddr[0];
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uint8_t* data = (uint8_t*)device_->m_axi_wdata[0].data();
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// check console output
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if (base_addr >= uint64_t(IO_COUT_ADDR)
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&& base_addr < (uint64_t(IO_COUT_ADDR) + IO_COUT_SIZE)) {
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&& base_addr < (uint64_t(IO_COUT_ADDR) + IO_COUT_SIZE)) {
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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if ((byteen >> i) & 0x1) {
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auto& ss_buf = print_bufs_[i];
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char c = data[i];
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ss_buf << c;
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@ -410,7 +410,7 @@ private:
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ss_buf.str("");
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}
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}
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}
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}
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} else {
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/*
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printf("%0ld: [sim] MEM Wr: addr=%0x, byteen=%0lx, data=", timestamp, base_addr, byteen);
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@ -420,26 +420,26 @@ private:
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printf("\n");
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*/
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[base_addr + i] = data[i];
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}
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}
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}
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auto mem_req = new mem_req_t();
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mem_req->tag = device_->m_axi_awid[0];
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mem_req->addr = device_->m_axi_awaddr[0];
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mem_req->addr = device_->m_axi_awaddr[0];
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mem_req->write = true;
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mem_req->ready = true;
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pending_mem_reqs_.emplace_back(mem_req);
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// send dram request
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ramulator::Request dram_req(
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ramulator::Request dram_req(
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device_->m_axi_awaddr[0],
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ramulator::Request::Type::WRITE,
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0
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);
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dram_queue_.push(dram_req);
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}
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}
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} else {
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// process reads
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auto mem_req = new mem_req_t();
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@ -451,7 +451,7 @@ private:
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pending_mem_reqs_.emplace_back(mem_req);
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// send dram request
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ramulator::Request dram_req(
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ramulator::Request dram_req(
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device_->m_axi_araddr[0],
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ramulator::Request::Type::READ,
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std::bind([&](ramulator::Request& dram_req, mem_req_t* mem_req) {
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@ -460,12 +460,12 @@ private:
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0
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);
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dram_queue_.push(dram_req);
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}
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}
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}
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}
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device_->m_axi_wready[0] = running_;
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device_->m_axi_awready[0] = running_;
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device_->m_axi_arready[0] = running_;
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device_->m_axi_arready[0] = running_;
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}
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#else
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@ -486,7 +486,7 @@ private:
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return;
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}
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// process memory responses
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// process memory responses
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if (mem_rd_rsp_active_
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&& device_->mem_rsp_valid && mem_rd_rsp_ready_) {
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mem_rd_rsp_active_ = false;
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@ -494,7 +494,7 @@ private:
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if (!mem_rd_rsp_active_) {
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if (!pending_mem_reqs_.empty()
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&& (*pending_mem_reqs_.begin())->ready) {
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device_->mem_rsp_valid = 1;
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device_->mem_rsp_valid = 1;
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auto mem_rsp_it = pending_mem_reqs_.begin();
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auto mem_rsp = *mem_rsp_it;
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/*
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@ -505,7 +505,7 @@ private:
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printf("\n");
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*/
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memcpy(device_->mem_rsp_data.data(), mem_rsp->block.data(), MEM_BLOCK_SIZE);
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device_->mem_rsp_tag = mem_rsp->tag;
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device_->mem_rsp_tag = mem_rsp->tag;
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pending_mem_reqs_.erase(mem_rsp_it);
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mem_rd_rsp_active_ = true;
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delete mem_rsp;
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@ -514,19 +514,19 @@ private:
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}
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}
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// process memory requests
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// process memory requests
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if (device_->mem_req_valid && running_) {
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uint64_t byte_addr = (device_->mem_req_addr * MEM_BLOCK_SIZE);
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if (device_->mem_req_rw) {
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if (device_->mem_req_rw) {
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// process writes
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uint64_t byteen = device_->mem_req_byteen;
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uint64_t byteen = device_->mem_req_byteen;
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uint8_t* data = (uint8_t*)(device_->mem_req_data.data());
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// check console output
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if (byte_addr >= uint64_t(IO_COUT_ADDR)
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&& byte_addr < (uint64_t(IO_COUT_ADDR) + IO_COUT_SIZE)) {
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&& byte_addr < (uint64_t(IO_COUT_ADDR) + IO_COUT_SIZE)) {
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for (int i = 0; i < IO_COUT_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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if ((byteen >> i) & 0x1) {
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auto& ss_buf = print_bufs_[i];
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char c = data[i];
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ss_buf << c;
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@ -535,7 +535,7 @@ private:
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ss_buf.str("");
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}
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}
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}
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}
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} else {
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/*
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printf("%0ld: [sim] MEM Wr: tag=%0lx, addr=%0x, byteen=%0lx, data=", timestamp, device_->mem_req_tag, byte_addr, byteen);
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@ -545,23 +545,23 @@ private:
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printf("\n");
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*/
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for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
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if ((byteen >> i) & 0x1) {
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if ((byteen >> i) & 0x1) {
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(*ram_)[byte_addr + i] = data[i];
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}
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}
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// send dram request
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ramulator::Request dram_req(
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ramulator::Request dram_req(
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byte_addr,
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ramulator::Request::Type::WRITE,
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0
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);
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dram_queue_.push(dram_req);
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}
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}
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} else {
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// process reads
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auto mem_req = new mem_req_t();
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mem_req->tag = device_->mem_req_tag;
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mem_req->tag = device_->mem_req_tag;
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mem_req->addr = byte_addr;
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mem_req->write = false;
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mem_req->ready = false;
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@ -571,7 +571,7 @@ private:
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//printf("%0ld: [sim] MEM Rd Req: addr=%0x, tag=%0lx\n", timestamp, byte_addr, device_->mem_req_tag);
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// send dram request
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ramulator::Request dram_req(
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ramulator::Request dram_req(
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byte_addr,
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ramulator::Request::Type::READ,
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std::bind([&](ramulator::Request& dram_req, mem_req_t* mem_req) {
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@ -581,7 +581,7 @@ private:
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);
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dram_queue_.push(dram_req);
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}
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}
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}
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device_->mem_req_ready = running_;
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}
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@ -625,8 +625,8 @@ private:
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private:
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typedef struct {
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bool ready;
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typedef struct {
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bool ready;
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std::array<uint8_t, MEM_BLOCK_SIZE> block;
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uint64_t addr;
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uint64_t tag;
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@ -663,7 +663,7 @@ private:
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///////////////////////////////////////////////////////////////////////////////
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Processor::Processor()
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Processor::Processor()
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: impl_(new Impl())
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{}
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@ -679,6 +679,6 @@ int Processor::run() {
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return impl_->run();
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}
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void Processor::write_dcr(uint32_t addr, uint32_t value) {
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return impl_->write_dcr(addr, value);
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void Processor::dcr_write(uint32_t addr, uint32_t value) {
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return impl_->dcr_write(addr, value);
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}
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