github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-24 05:47:35 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2024-10-15 02:27:07 -07:00
parent 03a1e25828
commit db98965f56
2 changed files with 147 additions and 325 deletions
Download patch file Download diff file Expand all files Collapse all files

470
hw/rtl/libs/VX_dp_ram.sv
View file

@ -19,7 +19,6 @@ module VX_dp_ram #(
parameter SIZE = 1,
parameter WRENW = 1,
parameter OUT_REG = 0,
parameter RADDR_REG = 0,
parameter LUTRAM = 0,
parameter NO_RWCHECK = 0,
parameter RW_ASSERT = 0,
@ -44,328 +43,174 @@ module VX_dp_ram #(
localparam WSELW = DATAW / WRENW;
`STATIC_ASSERT((WRENW * WSELW == DATAW), ("invalid parameter"))
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
if (INIT_FILE != "") begin : g_file \
initial $readmemh(INIT_FILE, ram); \
end else begin : g_value \
initial begin \
for (integer i = 0; i < SIZE; ++i) \
ram[i] = INIT_VALUE; \
end \
end \
`define RAM_INITIALIZATION \
if (INIT_ENABLE != 0) begin : g_init \
if (INIT_FILE != "") begin : g_file \
initial $readmemh(INIT_FILE, ram); \
end else begin : g_value \
initial begin \
for (integer i = 0; i < SIZE; ++i) begin : g_i \
ram[i] = INIT_VALUE; \
end \
end \
end \
end
`define RAM_WREN_BLOCK_ALTERA(__we__) \
reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1]; \
`RAM_INITIALIZATION \
always @(posedge clk) begin \
if (__we__) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end \
end
`define RAM_WREN_BLOCK_XILINX(__we__) \
reg [DATAW-1:0] ram [0:SIZE-1]; \
`RAM_INITIALIZATION \
always @(posedge clk) begin \
if (__we__) begin \
for (integer i = 0; i < WRENW; ++i) begin \
if (wren[i]) begin \
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \
end \
end \
end \
end
`define RAM_WRITE_BLOCK(__we__) \
reg [DATAW-1:0] ram [0:SIZE-1]; \
`RAM_INITIALIZATION \
always @(posedge clk) begin \
if (__we__) begin \
ram[waddr] <= wdata; \
end \
end
`define RAM_READ_BLOCK_OUT_REG(__re__) \
always @(posedge clk) begin \
if (__re__) begin \
if (RESET_OUT && reset) begin \
rdata_r <= INIT_VALUE; \
end else begin \
rdata_r <= ram[raddr]; \
end \
end \
end
`UNUSED_PARAM (RW_ASSERT)
`UNUSED_VAR (read)
`UNUSED_VAR (wren)
if (OUT_REG && !READ_ENABLE) begin : g_out_reg
`UNUSED_PARAM (NO_RWCHECK)
if (OUT_REG) begin : g_out_reg
reg [DATAW-1:0] rdata_r;
wire cs = read || write;
if (WRENW != 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
if (READ_ENABLE) begin : g_readen
if (WRENW != 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WREN_BLOCK_ALTERA(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end else begin : g_no_lutram
`RAM_WREN_BLOCK_ALTERA(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end
end else begin : g_no_lutram
reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
`else
// Not Quartus
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WREN_BLOCK_XILINX(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end else begin : g_no_lutram
`RAM_WREN_BLOCK_XILINX(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end
`endif
end else begin : g_no_writeen
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WRITE_BLOCK(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end else begin : g_no_lutram
`RAM_WRITE_BLOCK(write)
`RAM_READ_BLOCK_OUT_REG(read || write)
end
end
`else
// Not Quartus
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
end else begin : g_no_readen
if (WRENW != 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WREN_BLOCK_ALTERA(write)
`RAM_READ_BLOCK_OUT_REG(read)
end else begin : g_no_lutram
`RAM_WREN_BLOCK_ALTERA(write)
`RAM_READ_BLOCK_OUT_REG(read)
end
end else begin : g_no_lutram
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
`else
// Not Quartus
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WREN_BLOCK_XILINX(write)
`RAM_READ_BLOCK_OUT_REG(read)
end else begin : g_no_lutram
`RAM_WREN_BLOCK_XILINX(write)
`RAM_READ_BLOCK_OUT_REG(read)
end
end
`endif
end else begin : g_no_writeen
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write)
ram[waddr] <= wdata;
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
end
end else begin : g_no_lutram
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (cs) begin
if (write)
ram[waddr] <= wdata;
if (RESET_OUT && reset) begin
rdata_r <= INIT_VALUE;
end else begin
rdata_r <= ram[raddr];
end
end
`endif
end else begin : g_no_writeen
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM `RAM_WRITE_BLOCK(write)
`RAM_READ_BLOCK_OUT_REG(read)
end else begin : g_no_lutram
`RAM_WRITE_BLOCK(write)
`RAM_READ_BLOCK_OUT_REG(read)
end
end
end
assign rdata = rdata_r;
end else begin : g_no_out_reg
// OUT_REG==0 || READ_ENABLE=1
wire [DATAW-1:0] rdata_w;
reg [ADDRW-1:0] raddr_reg;
`ifdef SYNTHESIS
if (WRENW > 1) begin : g_writeen
`ifdef QUARTUS
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`USE_FAST_BRAM `RAM_WREN_BLOCK_ALTERA(write)
assign rdata = ram[raddr];
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`NO_RW_RAM_CHECK `RAM_WREN_BLOCK_ALTERA(write)
assign rdata = ram[raddr];
end else begin : g_rwcheck
reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`RAM_WREN_BLOCK_ALTERA(write)
assign rdata = ram[raddr];
end
end
`else
// default synthesis
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`USE_FAST_BRAM `RAM_WREN_BLOCK_XILINX(write)
assign rdata = ram[raddr];
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`NO_RW_RAM_CHECK `RAM_WREN_BLOCK_XILINX(write)
assign rdata = ram[raddr];
end else begin : g_rwcheck
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`RAM_WREN_BLOCK_XILINX(write)
assign rdata = ram[raddr];
end
end
`endif
end else begin : g_no_writeen
// (WRENW == 1)
if (LUTRAM != 0) begin : g_lutram
`USE_FAST_BRAM reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`USE_FAST_BRAM `RAM_WRITE_BLOCK(write)
assign rdata = ram[raddr];
end else begin : g_no_lutram
if (NO_RWCHECK != 0) begin : g_no_rwcheck
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`NO_RW_RAM_CHECK `RAM_WRITE_BLOCK(write)
assign rdata = ram[raddr];
end else begin : g_rwcheck
reg [DATAW-1:0] ram [0:SIZE-1];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (write) begin
ram[waddr] <= wdata;
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
assign rdata_w = ram[raddr];
`UNUSED_VAR (raddr_reg)
end
`RAM_WRITE_BLOCK(write)
assign rdata = ram[raddr];
end
end
end
@ -389,54 +234,33 @@ module VX_dp_ram #(
ram[waddr] <= ram_n;
end
end
if (read) begin
raddr_reg <= raddr;
end
end
if (RADDR_REG != 0) begin : g_rdata_async
assign rdata_w = ram[raddr_reg];
end else begin : g_rdata_sync
`UNUSED_VAR (raddr_reg)
if (!LUTRAM && NO_RWCHECK) begin : g_rdata_no_bypass
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
if (!LUTRAM && NO_RWCHECK) begin : g_rdata_no_bypass
reg [DATAW-1:0] prev_data;
reg [ADDRW-1:0] prev_waddr;
reg prev_write;
always @(posedge clk) begin
if (reset) begin
prev_write <= 0;
prev_data <= '0;
prev_waddr <= '0;
end else begin
prev_write <= write;
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
always @(posedge clk) begin
if (reset) begin
prev_write <= 0;
prev_data <= '0;
prev_waddr <= '0;
end else begin
prev_write <= write;
prev_data <= ram[waddr];
prev_waddr <= waddr;
end
assign rdata_w = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
if (RW_ASSERT) begin : g_rw_assert
`RUNTIME_ASSERT(~read || (rdata_w == ram[raddr]), ("%t: read after write hazard", $time))
end
end else begin : g_rdata_with_bypass
assign rdata_w = ram[raddr];
end
assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr];
if (RW_ASSERT) begin : g_rw_assert
`RUNTIME_ASSERT(~read || (rdata == ram[raddr]), ("%t: read after write hazard", $time))
end
end else begin : g_rdata_with_bypass
assign rdata = ram[raddr];
end
`endif
if (OUT_REG != 0) begin : g_rdata_req
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (READ_ENABLE && reset) begin
rdata_r <= INIT_VALUE;
end else if (!READ_ENABLE || read) begin
rdata_r <= rdata_w;
end
end
assign rdata = rdata_r;
end else begin : g_rdata_comb
assign rdata = rdata_w;
end
end
endmodule

2
hw/rtl/libs/VX_sp_ram.sv
View file

@ -26,7 +26,6 @@ module VX_sp_ram #(
parameter RESET_OUT = 0,
parameter READ_ENABLE = 0,
parameter INIT_ENABLE = 0,
parameter RADDR_REG = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
parameter ADDRW = `LOG2UP(SIZE)
@ -45,7 +44,6 @@ module VX_sp_ram #(
.SIZE (SIZE),
.WRENW (WRENW),
.OUT_REG (OUT_REG),
.RADDR_REG (RADDR_REG),
.LUTRAM (LUTRAM),
.NO_RWCHECK (NO_RWCHECK),
.RW_ASSERT (RW_ASSERT),