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minor update

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This commit is contained in:
Blaise Tine 2023-03-20 03:47:55 -04:00
parent bbf8756037
commit db9f424a64
1 changed files with 6 additions and 3 deletions
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9
hw/rtl/fpu_unit/VX_fpu_ncomp.sv
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@ -233,7 +233,7 @@ module VX_fpu_ncomp #(
end
3,4: begin
tmp_result[i] = fminmax_res[i];
tmp_fflags_NV[i].NV = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
tmp_fflags_NV[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
end
//5,6,7: MOVE
default: begin
@ -253,7 +253,7 @@ module VX_fpu_ncomp #(
assign stall = ~ready_out && valid_out;
wire fflags_NV;
wire [NUM_LANES-1:0] fflags_NV;
VX_pipe_register #(
.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + (NUM_LANES * 1)),
@ -267,6 +267,9 @@ module VX_fpu_ncomp #(
);
assign ready_in = ~stall;
assign fflags = {fflags_NV, 4'b0};
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign fflags[i] = {fflags_NV[i], 4'b0};
end
endmodule