mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
d81ce8b609
commit
e0905f8352
11 changed files with 133 additions and 123 deletions
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@ -62,7 +62,6 @@ case $i in
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;;
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--scope)
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SCOPE=1
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SCOPE_FLAG=-DSCOPE
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shift
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;;
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--perf)
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@ -130,7 +129,7 @@ case $APP in
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;;
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esac
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CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS -DL2_ENABLE=$L2 -DL3_ENABLE=$L3 $PERF_FLAG $SCOPE_FLAG"
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CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_THREADS=$THREADS -DL2_ENABLE=$L2 -DL3_ENABLE=$L3 $PERF_FLAG"
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echo "CONFIGS=$CONFIGS"
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@ -138,7 +137,12 @@ make -C $DRIVER_PATH clean
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if [ $DEBUG -eq 1 ]
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then
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DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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if [ $SCOPE -eq 1 ]
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then
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DEBUG=1 SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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else
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DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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fi
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if [ $HAS_ARGS -eq 1 ]
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then
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@ -147,7 +151,12 @@ then
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make -C $APP_PATH run-$DRIVER > run.log 2>&1
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fi
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else
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CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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if [ $SCOPE -eq 1 ]
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then
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SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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else
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CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA
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fi
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if [ $HAS_ARGS -eq 1 ]
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then
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@ -23,69 +23,44 @@ module VX_dcache_arb (
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localparam REQ_DATAW = `NUM_THREADS + 1 + `NUM_THREADS * `DWORD_SIZE + `NUM_THREADS * (32-`CLOG2(`DWORD_SIZE)) + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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//
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// input request buffer
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//
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VX_cache_core_req_if #(
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.NUM_REQS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_req_qual_if();
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wire core_req_valid;
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VX_skid_buffer #(
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.DATAW (REQ_DATAW)
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) req_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in ((| core_req_if.valid)),
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.data_in ({core_req_if.valid, core_req_if.rw, core_req_if.byteen, core_req_if.addr, core_req_if.data, core_req_if.tag}),
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.ready_in (core_req_if.ready),
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.valid_out (core_req_valid),
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.data_out ({core_req_qual_if.valid, core_req_qual_if.rw, core_req_qual_if.byteen, core_req_qual_if.addr, core_req_qual_if.data, core_req_qual_if.tag}),
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.ready_out (core_req_qual_if.ready)
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);
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//
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// select request
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//
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// select shared memory bus
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wire is_smem_addr = core_req_valid
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&& ({core_req_qual_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
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&& ({core_req_qual_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE));
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wire is_smem_addr = (| core_req_if.valid)
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&& ({core_req_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
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&& ({core_req_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE));
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// select io bus
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wire is_io_addr = core_req_valid
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&& ({core_req_qual_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
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wire is_io_addr = (| core_req_if.valid)
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&& ({core_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
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reg [2:0] req_select;
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reg req_ready;
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assign cache_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[0]}};
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assign cache_req_if.rw = core_req_qual_if.rw;
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assign cache_req_if.byteen = core_req_qual_if.byteen;
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assign cache_req_if.addr = core_req_qual_if.addr;
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assign cache_req_if.data = core_req_qual_if.data;
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assign cache_req_if.tag = core_req_qual_if.tag;
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assign cache_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[0]}};
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assign cache_req_if.rw = core_req_if.rw;
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assign cache_req_if.byteen = core_req_if.byteen;
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assign cache_req_if.addr = core_req_if.addr;
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assign cache_req_if.data = core_req_if.data;
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assign cache_req_if.tag = core_req_if.tag;
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assign smem_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[1]}};
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assign smem_req_if.rw = core_req_qual_if.rw;
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assign smem_req_if.byteen = core_req_qual_if.byteen;
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assign smem_req_if.addr = core_req_qual_if.addr;
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assign smem_req_if.data = core_req_qual_if.data;
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assign smem_req_if.tag = core_req_qual_if.tag;
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assign smem_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[1]}};
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assign smem_req_if.rw = core_req_if.rw;
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assign smem_req_if.byteen = core_req_if.byteen;
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assign smem_req_if.addr = core_req_if.addr;
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assign smem_req_if.data = core_req_if.data;
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assign smem_req_if.tag = core_req_if.tag;
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assign io_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[2]}};
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assign io_req_if.rw = core_req_qual_if.rw;
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assign io_req_if.byteen = core_req_qual_if.byteen;
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assign io_req_if.addr = core_req_qual_if.addr;
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assign io_req_if.data = core_req_qual_if.data;
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assign io_req_if.tag = core_req_qual_if.tag;
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assign io_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[2]}};
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assign io_req_if.rw = core_req_if.rw;
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assign io_req_if.byteen = core_req_if.byteen;
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assign io_req_if.addr = core_req_if.addr;
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assign io_req_if.data = core_req_if.data;
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assign io_req_if.tag = core_req_if.tag;
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assign core_req_qual_if.ready = req_ready;
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assign core_req_if.ready = req_ready;
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always @(*) begin
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req_select = 0;
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@ -30,72 +30,77 @@ module VX_instr_demux (
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// ALU unit
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wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU);
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wire alu_stall = alu_req_if.valid && ~alu_req_if.ready;
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wire alu_req_ready;
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wire is_br_op = `IS_BR_MOD(execute_if.op_mod);
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
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.R (1)
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) alu_pipe (
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.clk (clk),
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.reset (reset),
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.stall (alu_stall),
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.flush (1'b0),
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.data_in ({alu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({alu_req_if.valid, alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data})
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
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.REGISTER (1) // ALU has no back pressure, use a simple register
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) alu_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (alu_req_valid),
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.ready_in (alu_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `ALU_BR_OP(execute_if.op_type), is_br_op, execute_if.imm, execute_if.rs1_is_PC, execute_if.rs2_is_imm, execute_if.rd, execute_if.wb, tid, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({alu_req_if.wid, alu_req_if.tmask, alu_req_if.PC, alu_req_if.next_PC, alu_req_if.op_type, alu_req_if.is_br_op, alu_req_if.imm, alu_req_if.rs1_is_PC, alu_req_if.rs2_is_imm, alu_req_if.rd, alu_req_if.wb, alu_req_if.tid, alu_req_if.rs1_data, alu_req_if.rs2_data}),
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.valid_out (alu_req_if.valid),
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.ready_out (alu_req_if.ready)
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);
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// lsu unit
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wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU);
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wire lsu_stall = lsu_req_if.valid && ~lsu_req_if.ready;
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wire lsu_req_ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
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.R (1)
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) lsu_pipe (
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + 1 + `BYTEEN_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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) lsu_buffer (
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.clk (clk),
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.reset (reset),
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.stall (lsu_stall),
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.flush (1'b0),
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.data_in ({lsu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data})
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.valid_in (lsu_req_valid),
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.ready_in (lsu_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
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.valid_out (lsu_req_if.valid),
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.ready_out (lsu_req_if.ready)
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);
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// csr unit
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wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR);
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wire csr_stall = csr_req_if.valid && ~csr_req_if.ready;
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wire csr_req_ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32),
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.R (1)
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) csr_pipe (
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32)
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) csr_buffer (
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.clk (clk),
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.reset (reset),
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.stall (csr_stall),
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.flush (1'b0),
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.data_in ({csr_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}),
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.data_out ({csr_req_if.valid, csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data})
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.valid_in (csr_req_valid),
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.ready_in (csr_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `CSR_OP(execute_if.op_type), execute_if.imm[`CSR_ADDR_BITS-1:0], execute_if.rd, execute_if.wb, execute_if.rs2_is_imm, execute_if.rs1, gpr_rsp_if.rs1_data[0]}),
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.data_out ({csr_req_if.wid, csr_req_if.tmask, csr_req_if.PC, csr_req_if.op_type, csr_req_if.csr_addr, csr_req_if.rd, csr_req_if.wb, csr_req_if.rs2_is_imm, csr_req_if.rs1, csr_req_if.rs1_data}),
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.valid_out (csr_req_if.valid),
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.ready_out (csr_req_if.ready)
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);
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// mul unit
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`ifdef EXT_M_ENABLE
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wire mul_req_valid = execute_if.valid && (execute_if.ex_type == `EX_MUL);
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wire mul_stall = mul_req_if.valid && ~mul_req_if.ready;
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wire mul_req_ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
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.R (1)
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) mul_pipe (
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `MUL_BITS + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
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) mul_buffer (
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.clk (clk),
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.reset (reset),
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.stall (mul_stall),
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.flush (1'b0),
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.data_in ({mul_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({mul_req_if.valid, mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data})
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.valid_in (mul_req_valid),
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.ready_in (mul_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `MUL_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
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.data_out ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.op_type, mul_req_if.rd, mul_req_if.wb, mul_req_if.rs1_data, mul_req_if.rs2_data}),
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.valid_out (mul_req_if.valid),
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.ready_out (mul_req_if.ready)
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);
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`endif
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@ -103,18 +108,19 @@ module VX_instr_demux (
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`ifdef EXT_F_ENABLE
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wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU);
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wire fpu_stall = fpu_req_if.valid && ~fpu_req_if.ready;
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wire fpu_req_ready;
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VX_generic_register #(
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.N (1 + `NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)),
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.R (1)
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) fpu_pipe (
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VX_skid_buffer #(
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.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
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) fpu_buffer (
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.clk (clk),
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.reset (reset),
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.stall (fpu_stall),
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.flush (1'b0),
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.data_in ({fpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
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.data_out ({fpu_req_if.valid, fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data})
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.valid_in (fpu_req_valid),
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.ready_in (fpu_req_ready),
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.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, `FPU_OP(execute_if.op_type), execute_if.op_mod, execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, gpr_rsp_if.rs3_data}),
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.data_out ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.op_type, fpu_req_if.op_mod, fpu_req_if.rd, fpu_req_if.wb, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data}),
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.valid_out (fpu_req_if.valid),
|
||||
.ready_out (fpu_req_if.ready)
|
||||
);
|
||||
`else
|
||||
`UNUSED_VAR (gpr_rsp_if.rs3_data)
|
||||
|
|
@ -123,30 +129,31 @@ module VX_instr_demux (
|
|||
// gpu unit
|
||||
|
||||
wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU);
|
||||
wire gpu_stall = gpu_req_if.valid && ~gpu_req_if.ready;
|
||||
wire gpu_req_ready;
|
||||
|
||||
VX_generic_register #(
|
||||
.N (1 + `NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)),
|
||||
.R (1)
|
||||
) gpu_pipe (
|
||||
VX_skid_buffer #(
|
||||
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32))
|
||||
) gpu_buffer (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (gpu_stall),
|
||||
.flush (1'b0),
|
||||
.data_in ({gpu_req_valid, execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}),
|
||||
.data_out ({gpu_req_if.valid, gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data})
|
||||
.valid_in (gpu_req_valid),
|
||||
.ready_in (gpu_req_ready),
|
||||
.data_in ({execute_if.wid, execute_if.tmask, execute_if.PC, next_PC, `GPU_OP(execute_if.op_type), execute_if.rd, execute_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data[0]}),
|
||||
.data_out ({gpu_req_if.wid, gpu_req_if.tmask, gpu_req_if.PC, gpu_req_if.next_PC, gpu_req_if.op_type, gpu_req_if.rd, gpu_req_if.wb, gpu_req_if.rs1_data, gpu_req_if.rs2_data}),
|
||||
.valid_out (gpu_req_if.valid),
|
||||
.ready_out (gpu_req_if.ready)
|
||||
);
|
||||
|
||||
// can take next request?
|
||||
assign execute_if.ready = (!alu_stall && (execute_if.ex_type == `EX_ALU))
|
||||
|| (!lsu_stall && (execute_if.ex_type == `EX_LSU))
|
||||
|| (!csr_stall && (execute_if.ex_type == `EX_CSR))
|
||||
assign execute_if.ready = (alu_req_ready && (execute_if.ex_type == `EX_ALU))
|
||||
|| (lsu_req_ready && (execute_if.ex_type == `EX_LSU))
|
||||
|| (csr_req_ready && (execute_if.ex_type == `EX_CSR))
|
||||
`ifdef EXT_M_ENABLE
|
||||
|| (!mul_stall && (execute_if.ex_type == `EX_MUL))
|
||||
|| (mul_req_ready && (execute_if.ex_type == `EX_MUL))
|
||||
`endif
|
||||
`ifdef EXT_F_ENABLE
|
||||
|| (!fpu_stall && (execute_if.ex_type == `EX_FPU))
|
||||
|| (fpu_req_ready && (execute_if.ex_type == `EX_FPU))
|
||||
`endif
|
||||
|| (!gpu_stall && (execute_if.ex_type == `EX_GPU));
|
||||
|| (gpu_req_ready && (execute_if.ex_type == `EX_GPU));
|
||||
|
||||
endmodule
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fdiv
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fsqrt
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftoi
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_ftou
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_itof
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_utof
|
||||
// SystemVerilog created on Wed Sep 2 07:11:09 2020
|
||||
// SystemVerilog created on Wed Dec 9 01:17:51 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
|
||||
module VX_skid_buffer #(
|
||||
parameter DATAW = 1,
|
||||
parameter PASSTHRU = 0
|
||||
parameter PASSTHRU = 0,
|
||||
parameter REGISTER = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
|
@ -25,6 +26,24 @@ module VX_skid_buffer #(
|
|||
assign data_out = data_in;
|
||||
assign ready_in = ready_out;
|
||||
|
||||
end if (REGISTER) begin
|
||||
|
||||
wire stall = valid_out && ~ready_out;
|
||||
|
||||
VX_generic_register #(
|
||||
.N (1 + DATAW),
|
||||
.R (1)
|
||||
) pipe_reg (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (stall),
|
||||
.flush (1'b0),
|
||||
.data_in ({valid_in, data_in}),
|
||||
.data_out ({valid_out, data_out})
|
||||
);
|
||||
|
||||
assign ready_in = ~stall;
|
||||
|
||||
end else begin
|
||||
|
||||
reg [DATAW-1:0] data_out_r;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
create_clock -name {clk} -period "220 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||
create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
|
||||
|
||||
derive_pll_clocks -create_base_clocks
|
||||
derive_clock_uncertainty
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue