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minor updates
This commit is contained in:
Blaise Tine
parent
fb4f62bab9
commit
e214c0b2a8
3 changed files with 67 additions and 62 deletions
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@ -111,17 +111,33 @@ module VX_muldiv (
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wire mul_ready_in;
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wire mul_ready_out = ~stall_out;
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VX_serial_mul #(
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.A_WIDTH (`XLEN+1),
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.LANES (`NUM_THREADS),
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.SIGNED (1)
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) multiplier (
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wire mul_strode;
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wire mul_busy;
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VX_elastic_adapter mul_elastic_adapter (
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.valid_in (mul_valid_in),
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.ready_in (mul_ready_in),
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.valid_out (mul_valid_out),
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.ready_out (mul_ready_out),
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.strobe (mul_strode),
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.busy (mul_busy)
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);
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VX_serial_mul #(
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.A_WIDTH (`XLEN+1),
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.LANES (`NUM_THREADS),
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.SIGNED (1)
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) serial_mul (
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.clk (clk),
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.reset (reset),
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.strobe (mul_strode),
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.busy (mul_busy),
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.dataa (mul_in1),
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.datab (mul_in2),
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.result (mul_result_tmp)
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@ -142,7 +158,7 @@ module VX_muldiv (
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`XLEN:0] mul_in1 = {is_signed_mul_a && alu_in1[i][`XLEN-1], alu_in1[i]};
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wire [`XLEN:0] mul_in2 = {is_signed_mul_b && alu_in2[i][`XLEN-1], alu_in2[i]};
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wire [`XLEN:0] mul_in2 = {is_signed_mul_b && alu_in2[i][`XLEN-1], alu_in2[i]};
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VX_multiplier #(
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.A_WIDTH (`XLEN+1),
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@ -244,14 +260,10 @@ module VX_muldiv (
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wire [`NUM_THREADS-1:0][`XLEN-1:0] div_quotient, div_remainder;
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wire is_rem_op_out;
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wire is_div_w_out;
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wire div_strode;
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wire div_busy;
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VX_serial_div #(
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.WIDTHN (`XLEN),
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.WIDTHD (`XLEN),
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.WIDTHQ (`XLEN),
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.WIDTHR (`XLEN),
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.LANES (`NUM_THREADS)
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) divide (
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VX_elastic_adapter div_elastic_adapter (
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.clk (clk),
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.reset (reset),
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@ -261,6 +273,23 @@ module VX_muldiv (
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.valid_out (div_valid_out),
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.ready_out (div_ready_out),
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.strobe (div_strode),
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.busy (div_busy)
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);
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VX_serial_div #(
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.WIDTHN (`XLEN),
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.WIDTHD (`XLEN),
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.WIDTHQ (`XLEN),
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.WIDTHR (`XLEN),
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.LANES (`NUM_THREADS)
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) serial_div (
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.clk (clk),
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.reset (reset),
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.strobe (div_strode),
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.busy (div_busy),
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.is_signed (is_signed_op),
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.numer (div_in1),
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.denom (div_in2),
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@ -11,11 +11,8 @@ module VX_serial_div #(
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire ready_out,
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output wire valid_out,
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input wire strobe,
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output wire busy,
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input wire is_signed,
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input wire [LANES-1:0][WIDTHN-1:0] numer,
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@ -37,7 +34,7 @@ module VX_serial_div #(
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reg [LANES-1:0] inv_quot, inv_rem;
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reg [CNTRW-1:0] cntr;
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reg busy, done;
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reg busy_r;
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for (genvar i = 0; i < LANES; ++i) begin
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wire negate_numer = is_signed && numer[i][WIDTHN-1];
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@ -46,40 +43,32 @@ module VX_serial_div #(
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assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i];
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assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i];
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end
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wire push = valid_in && ready_in;
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wire pop = valid_out && ready_out;
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always @(posedge clk) begin
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if (reset) begin
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busy <= 0;
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done <= 0;
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busy_r <= 0;
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end else begin
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if (push) begin
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busy <= 1;
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if (strobe) begin
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busy_r <= 1;
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end
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if (busy && cntr == 0) begin
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busy <= 0;
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done <= 1;
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end
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if (pop) begin
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done <= 0;
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busy_r <= 0;
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end
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end
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cntr <= cntr - CNTRW'(1);
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if (push) begin
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if (strobe) begin
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cntr <= CNTRW'(WIDTHN-1);
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end
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end
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for (genvar i = 0; i < LANES; ++i) begin
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always @(posedge clk) begin
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if (push) begin
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if (strobe) begin
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working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
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denom_r[i] <= denom_qual[i];
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inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]);
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inv_rem[i] <= is_signed && numer[i][31];
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end else if (busy) begin
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end else if (busy_r) begin
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working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
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{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
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end
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@ -89,9 +78,8 @@ module VX_serial_div #(
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assign quotient[i] = inv_quot[i] ? -$signed(q) : q;
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assign remainder[i] = inv_rem[i] ? -$signed(r) : r;
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end
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assign ready_in = ~busy && ~done;
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assign valid_out = done;
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assign busy = busy_r;
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endmodule
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`TRACING_ON
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@ -15,11 +15,8 @@ module VX_serial_mul #(
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire ready_out,
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output wire valid_out,
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input wire strobe,
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output wire busy,
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input wire [LANES-1:0][A_WIDTH-1:0] dataa,
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input wire [LANES-1:0][B_WIDTH-1:0] datab,
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@ -36,29 +33,21 @@ module VX_serial_mul #(
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reg [LANES-1:0][P_WIDTH-1:0] p;
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reg [CNTRW-1:0] cntr;
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reg busy, done;
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wire push = valid_in && ready_in;
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wire pop = valid_out && ready_out;
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reg busy_r;
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always @(posedge clk) begin
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if (reset) begin
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busy <= 0;
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done <= 0;
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busy_r <= 0;
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end else begin
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if (push) begin
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busy <= 1;
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if (strobe) begin
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busy_r <= 1;
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end
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if (busy && cntr == 0) begin
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done <= 1;
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end
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if (pop) begin
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busy <= 0;
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done <= 0;
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if (busy_r && cntr == 0) begin
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busy_r <= 0;
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end
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end
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cntr <= cntr - CNTRW'(1);
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if (push) begin
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if (strobe) begin
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cntr <= CNTRW'(X_WIDTH-1);
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end
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end
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@ -67,7 +56,7 @@ module VX_serial_mul #(
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wire [X_WIDTH-1:0] axb = b[i][0] ? a[i] : '0;
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always @(posedge clk) begin
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if (push) begin
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if (strobe) begin
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if (SIGNED) begin
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a[i] <= X_WIDTH'($signed(dataa[i]));
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b[i] <= Y_WIDTH'($signed(datab[i]));
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@ -76,7 +65,7 @@ module VX_serial_mul #(
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b[i] <= datab[i];
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end
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p[i] <= 0;
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end else if (busy) begin
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end else if (busy_r) begin
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b[i] <= (b[i] >> 1);
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p[i][Y_WIDTH-2:0] <= p[i][Y_WIDTH-1:1];
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if (SIGNED) begin
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@ -99,8 +88,7 @@ module VX_serial_mul #(
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end
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`UNUSED_VAR (p)
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assign ready_in = ~busy && ~done;
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assign valid_out = done;
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assign busy = busy_r;
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endmodule
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`TRACING_ON
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