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https://github.com/vortexgpgpu/vortex.git
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bank area optimization
This commit is contained in:
Blaise Tine
parent
5392395fba
commit
e26cfab04d
2 changed files with 43 additions and 48 deletions
64
hw/rtl/cache/VX_bank.v
vendored
64
hw/rtl/cache/VX_bank.v
vendored
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@ -149,7 +149,7 @@ module VX_bank #(
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wire [NUM_PORTS-1:0] pmask_st0, pmask_st1;
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wire [NUM_PORTS-1:0][CORE_TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire [`CACHE_LINE_WIDTH-1:0] rdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1;
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wire valid_st0, valid_st1;
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wire is_fill_st0, is_fill_st1;
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@ -198,27 +198,6 @@ module VX_bank #(
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end
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`endif
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wire [`CACHE_LINE_WIDTH-1:0] creq_line_data;
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if (`WORDS_PER_LINE > 1) begin
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if (NUM_PORTS > 1) begin
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reg [`CACHE_LINE_WIDTH-1:0] creq_line_data_r;
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always @(*) begin
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creq_line_data_r = 'x;
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if (creq_pmask[p]) begin
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creq_line_data_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data[p];
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end
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end
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end
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assign creq_line_data = creq_line_data_r;
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end else begin
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assign creq_line_data = {`WORDS_PER_LINE{creq_data}};
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end
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end else begin
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assign creq_line_data = creq_data;
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + NUM_PORTS * (WORD_SELECT_BITS + WORD_SIZE + `REQS_BITS + 1 + CORE_TAG_WIDTH) + MSHR_ADDR_WIDTH),
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.RESETW (1)
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@ -233,7 +212,7 @@ module VX_bank #(
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mshr_enable,
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creq_fire && creq_rw,
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mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
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(mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : creq_line_data,
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(mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : `CACHE_LINE_WIDTH'(creq_data),
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mshr_enable ? mshr_wsel : creq_wsel,
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creq_byteen,
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mshr_enable ? mshr_tid : creq_tid,
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@ -315,23 +294,36 @@ module VX_bank #(
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wire mreq_push_st1 = (read_st1 && miss_st1 && !mshr_pending_st1)
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|| write_st1;
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wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1;
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wire [`CACHE_LINE_WIDTH-1:0] line_wdata_st1;
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wire [CACHE_LINE_SIZE-1:0] line_byteen_st1;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data_st1 = wdata_st1[0 +: NUM_PORTS * `WORD_WIDTH];
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if (`WORDS_PER_LINE > 1) begin
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reg [`CACHE_LINE_WIDTH-1:0] line_wdata_r;
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reg [CACHE_LINE_SIZE-1:0] line_byteen_r;
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always @(*) begin
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line_byteen_r = 0;
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if ((NUM_PORTS == 1) || pmask_st1[p]) begin
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line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
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line_wdata_r = 'x;
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line_byteen_r = 0;
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if (NUM_PORTS > 1) begin
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if (creq_pmask[p]) begin
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line_wdata_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data_st1[p];
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line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
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end
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end
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end else begin
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line_wdata_r = {`WORDS_PER_LINE{creq_data_st1}};
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line_byteen_r[wsel_st1[0] * WORD_SIZE +: WORD_SIZE] = byteen_st1[0];
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end
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end
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assign line_wdata_st1 = line_wdata_r;
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assign line_byteen_st1 = line_byteen_r;
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end else begin
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assign line_byteen_st1 = byteen_st1;
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`UNUSED_VAR (wsel_st1)
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end
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assign line_wdata_st1 = creq_data_st1;
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assign line_byteen_st1 = byteen_st1;
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end
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VX_data_access #(
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.BANK_ID (BANK_ID),
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@ -356,13 +348,14 @@ module VX_bank #(
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// reading
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.readen (valid_st1 && read_st1),
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.rdata (rdata_st1),
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.read_data (rdata_st1),
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// writing
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.writeen (valid_st1 && writeen_st1),
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.is_fill (is_fill_st1),
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.byteen (line_byteen_st1),
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.wdata (wdata_st1)
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.byteen (line_byteen_st1),
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.write_data (line_wdata_st1),
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.fill_data (wdata_st1)
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);
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wire mshr_allocate = creq_fire && ~creq_rw;
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@ -482,6 +475,7 @@ module VX_bank #(
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assign mreq_addr = addr_st1;
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assign mreq_id = mshr_id_st1;
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assign mreq_wsel = wsel_st1;
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assign mreq_data = creq_data_st1;
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if (NUM_PORTS > 1) begin
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for (genvar p = 0; p < NUM_PORTS; ++p) begin
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@ -490,10 +484,6 @@ module VX_bank #(
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end else begin
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assign mreq_byteen[0] = byteen_st1[0];
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end
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for (genvar p = 0; p < NUM_PORTS; ++p) begin
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assign mreq_data[p] = wdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
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end
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VX_fifo_queue #(
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.DATAW (1 + `LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_PORTS * (WORD_SIZE + WORD_SELECT_BITS + `WORD_WIDTH)),
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27
hw/rtl/cache/VX_data_access.v
vendored
27
hw/rtl/cache/VX_data_access.v
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@ -32,13 +32,14 @@ module VX_data_access #(
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// reading
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input wire readen,
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output wire [`CACHE_LINE_WIDTH-1:0] rdata,
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output wire [`CACHE_LINE_WIDTH-1:0] read_data,
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// writing
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input wire writeen,
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input wire is_fill,
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input wire [CACHE_LINE_SIZE-1:0] byteen,
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input wire [`CACHE_LINE_WIDTH-1:0] wdata
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input wire [`CACHE_LINE_WIDTH-1:0] write_data,
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input wire [`CACHE_LINE_WIDTH-1:0] fill_data
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);
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`UNUSED_PARAM (CACHE_ID)
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@ -50,16 +51,20 @@ module VX_data_access #(
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localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
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wire [`LINE_SELECT_BITS-1:0] line_addr;
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wire [BYTEENW-1:0] byte_enable;
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wire [`CACHE_LINE_WIDTH-1:0] wdata;
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wire [BYTEENW-1:0] wren;
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assign line_addr = addr[`LINE_SELECT_BITS-1:0];
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if (WRITE_ENABLE) begin
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assign byte_enable = is_fill ? {BYTEENW{1'b1}} : byteen;
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assign wren = is_fill ? {BYTEENW{writeen}} : (byteen & {BYTEENW{writeen}});
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assign wdata = is_fill ? fill_data : write_data;
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end else begin
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`UNUSED_VAR (byteen)
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`UNUSED_VAR (is_fill)
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assign byte_enable = 1'b1;
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`UNUSED_VAR (byteen)
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`UNUSED_VAR (write_data)
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assign wren = writeen;
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assign wdata = fill_data;
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end
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VX_sp_ram #(
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@ -70,10 +75,10 @@ module VX_data_access #(
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) data_store (
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.clk (clk),
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.addr (line_addr),
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.wren ({BYTEENW{writeen}} & byte_enable),
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.wren (wren),
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.wdata (wdata),
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.rden (1'b1),
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.rdata (rdata)
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.rdata (read_data)
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);
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`UNUSED_VAR (stall)
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@ -82,13 +87,13 @@ module VX_data_access #(
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always @(posedge clk) begin
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if (writeen && ~stall) begin
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if (is_fill) begin
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dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wdata);
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dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);
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end else begin
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dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wdata);
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dpi_trace("%d: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, write_data);
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end
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end
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if (readen && ~stall) begin
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dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, rdata);
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dpi_trace("%d: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, line_addr, read_data);
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end
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end
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`endif
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