Force miss_add init ready to 1 when core req matches with mrvq entry, regardless of hit/miss

hw/rtl/cache/VX_bank.v

@@ -104,6 +104,35 @@ module VX_bank #(
     input  wire                                   snp_rsp_ready
 );
 
+`DEBUG_BEGIN
+    wire[31:0]           debug_use_pc_st0;
+    wire[1:0]            debug_wb_st0;
+    wire[4:0]            debug_rd_st0;
+    wire[`NW_BITS-1:0]   debug_warp_num_st0;
+    wire[2:0]            debug_mem_read_st0;    
+    wire[2:0]            debug_mem_write_st0;
+    wire[`REQS_BITS-1:0] debug_tid_st0;
+
+
+    wire[31:0]           debug_use_pc_st1e;
+    wire[1:0]            debug_wb_st1e;
+    wire[4:0]            debug_rd_st1e;
+    wire[`NW_BITS-1:0]   debug_warp_num_st1e;
+    wire[2:0]            debug_mem_read_st1e;    
+    wire[2:0]            debug_mem_write_st1e;
+    wire[`REQS_BITS-1:0] debug_tid_st1e;
+
+
+    wire[31:0]           debug_use_pc_st2;
+    wire[1:0]            debug_wb_st2;
+    wire[4:0]            debug_rd_st2;
+    wire[`NW_BITS-1:0]   debug_warp_num_st2;
+    wire[2:0]            debug_mem_read_st2;    
+    wire[2:0]            debug_mem_write_st2;
+    wire[`REQS_BITS-1:0] debug_tid_st2;
+`DEBUG_END
+
+
     wire snrq_pop;
     wire snrq_empty;
     wire snrq_full;
@@ -210,11 +239,9 @@ module VX_bank #(
     wire [`BYTE_EN_BITS-1:0]              mrvq_mem_write_st0;
     wire                                  mrvq_is_snp_st0;
 
-`DEBUG_BEGIN
     wire                                  mrvq_pending_hazard_st1e;
     wire                                  st2_pending_hazard_st1e;
     wire                                  force_request_miss_st1e;
-`DEBUG_END
 
     wire[`LINE_ADDR_WIDTH-1:0]            miss_add_addr;
     wire[`BASE_ADDR_BITS-1:0]             miss_add_wsel;
@@ -312,6 +339,10 @@ module VX_bank #(
 
     assign qual_from_mrvq_st0 = mrvq_pop;
 
+`DEBUG_BEGIN
+    assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0;
+`DEBUG_END
+
     VX_generic_register #(
         .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
     ) s0_1_c0 (
@@ -404,6 +435,10 @@ module VX_bank #(
         .mrvq_init_ready_state_st1e(mrvq_init_ready_state_st1e)
     );
 
+`DEBUG_BEGIN
+    assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
+`DEBUG_END
+
     wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
 
     wire                            valid_st2;    
@@ -431,6 +466,10 @@ module VX_bank #(
         .out ({mrvq_init_ready_state_st2,  snp_to_mrvq_st2 , is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2                   , valid_st2        , addr_st2                  , wsel_st2,                   writeword_st2                  , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2                  })
     );    
 
+`DEBUG_BEGIN
+    assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2;
+`DEBUG_END
+
     // Enqueue to miss reserv if it's a valid miss
     wire miss_add_because_miss    = valid_st2 && !is_snp_st2 && miss_st2;
     wire miss_add_because_pending = snp_to_mrvq_st2;

hw/rtl/cache/VX_cache.v

@@ -127,6 +127,16 @@ module VX_cache #(
     output wire [NUM_SNP_REQUESTS-1:0]      snp_fwdin_ready
 );
 
+`DEBUG_BEGIN
+    wire[31:0]           debug_core_req_use_pc;
+    wire[1:0]            debug_core_req_wb;
+    wire[4:0]            debug_core_req_rd;
+    wire[`NW_BITS-1:0]   debug_core_req_warp_num;
+
+    assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
+
+`DEBUG_END
+
     wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0]      per_bank_valids;
 
     wire [NUM_BANKS-1:0]                        per_bank_core_req_ready;

hw/rtl/cache/VX_tag_data_access.v

@@ -244,7 +244,9 @@ module VX_tag_data_access #(
     
     assign snp_to_mrvq_st1e           = valid_req_st1e && is_snp_st1e && force_request_miss_st1e;
     
-    assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || force_core_miss;
+    // The second term is basically saying always make an entry ready if there's already antoher entry waiting, even if you yourself see a miss
+    assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || (force_request_miss_st1e && !is_snp_st1e && !writefill_st1e && valid_req_st1e);
+    // assign mrvq_init_ready_state_st1e = snp_to_mrvq_st1e || force_core_miss;
 
     assign miss_st1e           = real_miss || snoop_hit_no_pending || force_core_miss;
     assign dirty_st1e          = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;