mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
xilinx xrt platforms configuration
This commit is contained in:
Blaise Tine
parent
8bb5e5ab8a
commit
e38c2c1fba
18 changed files with 167 additions and 136 deletions
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@ -275,9 +275,9 @@ config2()
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# test single-bank DRAM
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CONFIGS="-DPLATFORM_MEMORY_BANKS=1" ./ci/blackbox.sh --driver=opae --app=mstress
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# test 27-bit DRAM address
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CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=opae --app=mstress
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CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=27" ./ci/blackbox.sh --driver=xrt --app=mstress
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# test 33-bit DRAM address
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CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=opae --app=mstress
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CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=xrt --app=mstress
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echo "configuration-2 tests done!"
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}
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@ -31,7 +31,7 @@
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//`include "platform_afu_top_config.vh"
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`ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH
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`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH `PLATFORM_MEMORY_ADDR_WIDTH
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`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH (`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_DATA_WIDTH/8))
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`endif
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`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH
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@ -96,12 +96,10 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
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localparam STATE_DCR_WRITE = 4;
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localparam STATE_WIDTH = `CLOG2(STATE_DCR_WRITE+1);
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localparam BANK_BYTE_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH + `CLOG2(`PLATFORM_MEMORY_DATA_WIDTH/8);
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wire [127:0] afu_id = `AFU_ACCEL_UUID;
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wire [63:0] dev_caps = {8'b0,
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5'(BANK_BYTE_ADDR_WIDTH-16),
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5'(`PLATFORM_MEMORY_ADDR_WIDTH-16),
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3'(`CLOG2(`PLATFORM_MEMORY_BANKS)),
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8'(`LMEM_ENABLED ? `LMEM_LOG_SIZE : 0),
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16'(`NUM_CORES * `NUM_CLUSTERS),
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@ -119,9 +119,6 @@ module VX_afu_ctrl #(
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ADDR_SCP_1 = 8'h2C,
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`endif
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ADDR_MEM_0 = 8'h30,
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ADDR_MEM_1 = 8'h34,
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ADDR_BITS = 8;
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localparam
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@ -22,7 +22,7 @@ module vortex_afu #(
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parameter C_M_AXI_MEM_ADDR_WIDTH = 64,
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parameter C_M_AXI_MEM_NUM_BANKS = 1
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`else
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parameter C_M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH + $clog(`PLATFORM_MEMORY_DATA_WIDTH/8),
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parameter C_M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH,
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parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_BANKS
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`endif
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) (
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@ -19,7 +19,7 @@
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`endif
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`ifndef PLATFORM_MEMORY_ADDR_WIDTH
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`define PLATFORM_MEMORY_ADDR_WIDTH 25
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`define PLATFORM_MEMORY_ADDR_WIDTH 31
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`endif
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`ifndef PLATFORM_MEMORY_DATA_WIDTH
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@ -12,9 +12,9 @@ ifeq (,$(findstring PLATFORM_MEMORY_BANKS,$(CONFIGS)))
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endif
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ifeq (,$(findstring PLATFORM_MEMORY_ADDR_WIDTH,$(CONFIGS)))
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ifeq ($(XLEN),64)
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CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=41
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CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=47
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else
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CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=25
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CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=31
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endif
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endif
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ifeq (,$(findstring PLATFORM_MEMORY_DATA_WIDTH,$(CONFIGS)))
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@ -98,7 +98,7 @@ ifdef PERF
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endif
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# ast dump flags
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XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) $(RTL_PKGS) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DPLATFORM_PROVIDES_LOCAL_MEMORY -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=26 -DPLATFORM_MEMORY_DATA_WIDTH=512 -DPLATFORM_MEMORY_BURST_CNT_WIDTH=4 -DNOPAE -DSV_DPI
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XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) $(RTL_PKGS) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DPLATFORM_PROVIDES_LOCAL_MEMORY -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32 -DPLATFORM_MEMORY_DATA_WIDTH=512 -DPLATFORM_MEMORY_BURST_CNT_WIDTH=4 -DNOPAE -DSV_DPI
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all: swconfig ip-gen setup build
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@ -76,6 +76,7 @@ CONFIGS += $(CONFIGS_$(NUM_CORES)c)
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# include sources
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RTL_PKGS = $(RTL_DIR)/VX_gpu_pkg.sv $(RTL_DIR)/fpu/VX_fpu_pkg.sv
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RTL_PKGS += $(RTL_DIR)/tex/VX_tex_pkg.sv $(RTL_DIR)/raster/VX_raster_pkg.sv $(RTL_DIR)/om/VX_om_pkg.sv
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FPU_INCLUDE = -I$(RTL_DIR)/fpu
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ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
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RTL_PKGS += $(THIRD_PARTY_DIR)/cvfpu/src/fpnew_pkg.sv $(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src/cf_math_pkg $(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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@ -91,18 +92,8 @@ RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(OM_INCLUDE)
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VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
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VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
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ifeq ($(DEV_ARCH), zynquplus)
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# ztnq
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else ifeq ($(DEV_ARCH), versal)
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# versal
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else
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# alveo
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ifneq ($(findstring xilinx_u55c,$(XSA)),)
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
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else
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
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endif
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endif
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# load platform settings
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include $(SRC_DIR)/platforms.mk
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VPP_FLAGS += --report_level 2
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VPP_FLAGS += --config $(SRC_DIR)/vitis.ini
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@ -173,8 +164,12 @@ scope-json: $(BUILD_DIR)/scope.json
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$(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/scope.py vortex.xml -o scope.json
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gen-xml:
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$(BUILD_DIR)/kernel.xml:
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SRC_DIR)/gen_xml.py -n $(M_AXI_NUM_BANKS) -d $(M_AXI_DATA_WIDTH) -a $(M_AXI_ADDRESS_WIDTH) -o kernel.xml
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gen-xo: $(XO_CONTAINER)
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$(XO_CONTAINER): $(BUILD_DIR)/sources.txt
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$(XO_CONTAINER): $(BUILD_DIR)/sources.txt $(BUILD_DIR)/kernel.xml
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mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source $(SRC_DIR)/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
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gen-bin: $(XCLBIN_CONTAINER)
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75
hw/syn/xilinx/xrt/gen_xml.py
Normal file
75
hw/syn/xilinx/xrt/gen_xml.py
Normal file
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@ -0,0 +1,75 @@
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#!/usr/bin/env python3
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# Copyright © 2019-2023
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import argparse
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import xml.etree.ElementTree as ET
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from xml.dom import minidom
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def prettify(elem):
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"""Return a pretty-printed XML string for the Element."""
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rough_string = ET.tostring(elem, 'utf-8')
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reparsed = minidom.parseString(rough_string)
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return reparsed.toprettyxml(indent=" ")
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def generate_xml(numbanks, datawidth, addresswidth, offset, output_file):
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root = ET.Element("root", versionMajor="1", versionMinor="6")
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kernel = ET.SubElement(root, "kernel", name="vortex_afu", language="ip_c",
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vlnv="mycompany.com:kernel:vortex_afu:1.0",
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attributes="", preferredWorkGroupSizeMultiple="0",
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workGroupSize="1", interrupt="true")
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ports = ET.SubElement(kernel, "ports")
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# control ports
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ET.SubElement(ports, "port", name="s_axi_ctrl", mode="slave", range="0x1000", dataWidth="32", portType="addressable", base="0x0")
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# memory ports
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for i in range(numbanks):
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port_name = f"m_axi_mem_{i}"
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ET.SubElement(ports, "port", name=port_name, mode="master", range=f"0x{(1 << addresswidth) - 1:X}", dataWidth=str(datawidth), portType="addressable", base=f"0x0")
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args = ET.SubElement(kernel, "args")
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# control args
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ET.SubElement(args, "arg", name="dev", addressQualifier="0", id="0", port="s_axi_ctrl", size="0x4", offset="0x010", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="isa", addressQualifier="0", id="1", port="s_axi_ctrl", size="0x4", offset="0x018", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="dcr", addressQualifier="0", id="2", port="s_axi_ctrl", size="0x4", offset="0x020", type="uint", hostOffset="0x0", hostSize="0x4")
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ET.SubElement(args, "arg", name="scp", addressQualifier="0", id="3", port="s_axi_ctrl", size="0x4", offset="0x028", type="uint", hostOffset="0x0", hostSize="0x4")
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# memory args
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for i in range(numbanks):
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arg_name = f"mem_{i}"
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ET.SubElement(args, "arg", name=arg_name, addressQualifier="1", id=str(4 + i),
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port=f"m_axi_mem_{i}", size="0x8", offset=f"0x{offset + (i * 8):X}",
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type="int*", hostOffset="0x0", hostSize="0x8")
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# Pretty-print and write the XML to file
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with open(output_file, "w") as f:
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f.write(prettify(root))
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def main():
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parser = argparse.ArgumentParser(description="Kernel Configuration File Generator")
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parser.add_argument("-n", "--numbanks", type=int, default=1, help="Number of AXI memory banks")
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parser.add_argument("-d", "--datawidth", type=int, default=512, help="Data width of the AXI memory ports")
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parser.add_argument("-a", "--addresswidth", type=int, default=28, help="Address width of the AXI memory ports")
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parser.add_argument("-x", "--offset", type=lambda x: int(x, 0), default=0x30, help="Starting offset for kernel args (hex)")
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parser.add_argument("-o", "--output", type=str, default="kernel.xml", help="Output XML file name")
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args = parser.parse_args()
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# Call the generate function
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generate_xml(args.numbanks, args.datawidth, args.addresswidth, args.offset, args.output)
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if __name__ == "__main__":
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main()
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@ -37,4 +37,4 @@ set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
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set argc 4
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source ${script_path}/package_kernel.tcl
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package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel"
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package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel" -kernel_xml ${build_dir}/kernel.xml
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@ -41,14 +41,27 @@ set vdefines_list [lindex $vlist 2]
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#puts ${vincludes_list}
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#puts ${vdefines_list}
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# find if chipscope is enabled
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set chipscope 0
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set num_banks 1
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set merged_mem_if 0
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# parse vdefines_list for configuration parameters
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foreach def $vdefines_list {
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set fields [split $def "="]
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set name [lindex $fields 0]
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if { $name == "CHIPSCOPE" } {
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set chipscope 1
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}
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if { $name == "PLATFORM_MEMORY_BANKS" } {
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set num_banks [lindex $fields 1]
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}
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if { $name == "PLATFORM_MERGED_MEMORY_INTERFACE" } {
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set merged_mem_if 1
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}
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}
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if { $merged_mem_if == 1 } {
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set num_banks 1
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}
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create_project -force kernel_pack $path_to_tmp_project
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@ -143,108 +156,10 @@ foreach up [ipx::get_user_parameters] {
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ipx::associate_bus_interfaces -busif s_axi_ctrl -clock ap_clk $core
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for {set i 0} {$i < 1} {incr i} {
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for {set i 0} {$i < $num_banks} {incr i} {
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ipx::associate_bus_interfaces -busif m_axi_mem_$i -clock ap_clk $core
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}
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set mem_map [::ipx::add_memory_map -quiet "s_axi_ctrl" $core]
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set addr_block [::ipx::add_address_block -quiet "reg0" $mem_map]
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set reg [::ipx::add_register "CTRL" $addr_block]
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set_property description "Control signals" $reg
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set_property address_offset 0x000 $reg
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set_property size 32 $reg
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set field [ipx::add_field AP_START $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {0} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_start'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field AP_DONE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {1} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_done'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_IDLE $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {2} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_idle'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AP_READY $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {3} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'ap_ready'.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field RESERVED_1 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {4} $field
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set_property BIT_WIDTH {3} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set field [ipx::add_field AUTO_RESTART $reg]
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set_property ACCESS {read-write} $field
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set_property BIT_OFFSET {7} $field
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set_property BIT_WIDTH {1} $field
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set_property DESCRIPTION {Control signal Register for 'auto_restart'.} $field
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set_property MODIFIED_WRITE_VALUE {modify} $field
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set field [ipx::add_field RESERVED_2 $reg]
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set_property ACCESS {read-only} $field
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set_property BIT_OFFSET {8} $field
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set_property BIT_WIDTH {24} $field
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set_property DESCRIPTION {Reserved. 0s on read.} $field
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set_property READ_ACTION {modify} $field
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set reg [::ipx::add_register "GIER" $addr_block]
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set_property description "Global Interrupt Enable Register" $reg
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set_property address_offset 0x004 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_IER" $addr_block]
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set_property description "IP Interrupt Enable Register" $reg
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set_property address_offset 0x008 $reg
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set_property size 32 $reg
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set reg [::ipx::add_register "IP_ISR" $addr_block]
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set_property description "IP Interrupt Status Register" $reg
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set_property address_offset 0x00C $reg
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set_property size 32 $reg
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set reg [::ipx::add_register -quiet "DEV" $addr_block]
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set_property address_offset 0x010 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "ISA" $addr_block]
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set_property address_offset 0x01C $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "DCR" $addr_block]
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set_property address_offset 0x028 $reg
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set_property size [expr {8*8}] $reg
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set reg [::ipx::add_register -quiet "SCP" $addr_block]
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set_property address_offset 0x034 $reg
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set_property size [expr {8*8}] $reg
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for {set i 0} {$i < 1} {incr i} {
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set reg [::ipx::add_register -quiet "MEM_$i" $addr_block]
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set_property address_offset [expr {0x040 + $i * 12}] $reg
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set_property size [expr {8*8}] $reg
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set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
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set_property value m_axi_mem_$i $regparam
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}
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set_property slave_memory_map_ref "s_axi_ctrl" [::ipx::get_bus_interfaces -of $core "s_axi_ctrl"]
|
||||
|
||||
set_property xpm_libraries {XPM_CDC XPM_MEMORY XPM_FIFO} $core
|
||||
set_property sdx_kernel true $core
|
||||
set_property sdx_kernel_type rtl $core
|
||||
|
|
|
|||
51
hw/syn/xilinx/xrt/platforms.mk
Normal file
51
hw/syn/xilinx/xrt/platforms.mk
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# Platform specific configurations
|
||||
# Add your platform specific configurations here
|
||||
|
||||
M_AXI_NUM_BANKS := 1
|
||||
M_AXI_DATA_WIDTH := 512
|
||||
M_AXI_ADDRESS_WIDTH := 32
|
||||
|
||||
ifeq ($(DEV_ARCH), zynquplus)
|
||||
# zynquplus
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32
|
||||
else ifeq ($(DEV_ARCH), versal)
|
||||
# versal
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32
|
||||
ifneq ($(findstring xilinx_vck5000,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_OFFSET=40'hC000000000
|
||||
endif
|
||||
else
|
||||
# alveo
|
||||
ifneq ($(findstring xilinx_u55c,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=32 -DPLATFORM_MEMORY_ADDR_WIDTH=28
|
||||
#VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:31]
|
||||
#CONFIGS += -DPLATFORM_MERGED_MEMORY_INTERFACE
|
||||
VPP_FLAGS += $(foreach i,$(shell seq 0 31), --connectivity.sp vortex_afu_1.m_axi_mem_$(i):HBM[$(i)])
|
||||
M_AXI_NUM_BANKS := 32
|
||||
M_AXI_ADDRESS_WIDTH := 28
|
||||
else ifneq ($(findstring xilinx_u50,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=16 -DPLATFORM_MEMORY_ADDR_WIDTH=28
|
||||
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
|
||||
M_AXI_NUM_BANKS := 16
|
||||
M_AXI_ADDRESS_WIDTH := 28
|
||||
else ifneq ($(findstring xilinx_u280,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=16 -DPLATFORM_MEMORY_ADDR_WIDTH=28
|
||||
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem_0:HBM[0:15]
|
||||
M_AXI_NUM_BANKS := 16
|
||||
M_AXI_ADDRESS_WIDTH := 28
|
||||
else ifneq ($(findstring xilinx_u250,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=34
|
||||
M_AXI_NUM_BANKS := 4
|
||||
M_AXI_ADDRESS_WIDTH := 34
|
||||
else ifneq ($(findstring xilinx_u200,$(XSA)),)
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=4 -DPLATFORM_MEMORY_ADDR_WIDTH=34
|
||||
M_AXI_NUM_BANKS := 4
|
||||
M_AXI_ADDRESS_WIDTH := 34
|
||||
else
|
||||
CONFIGS += -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32
|
||||
M_AXI_NUM_BANKS := 1
|
||||
M_AXI_ADDRESS_WIDTH := 32
|
||||
endif
|
||||
endif
|
||||
|
||||
CONFIGS += -DPLATFORM_MEMORY_DATA_WIDTH=$(M_AXI_DATA_WIDTH)
|
||||
|
|
@ -37,9 +37,9 @@ ifeq (,$(findstring PLATFORM_MEMORY_BANKS,$(CONFIGS)))
|
|||
endif
|
||||
ifeq (,$(findstring PLATFORM_MEMORY_ADDR_WIDTH,$(CONFIGS)))
|
||||
ifeq ($(XLEN),64)
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=41
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=47
|
||||
else
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=25
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=31
|
||||
endif
|
||||
endif
|
||||
ifeq (,$(findstring PLATFORM_MEMORY_DATA_WIDTH,$(CONFIGS)))
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@ public:
|
|||
ram_ = new RAM(0, RAM_PAGE_SIZE);
|
||||
|
||||
// calculate memory bank size
|
||||
mem_bank_size_ = (1ull << PLATFORM_MEMORY_ADDR_WIDTH) * PLATFORM_MEMORY_DATA_SIZE;
|
||||
mem_bank_size_ = 1ull << PLATFORM_MEMORY_ADDR_WIDTH;
|
||||
|
||||
// reset the device
|
||||
this->reset();
|
||||
|
|
|
|||
|
|
@ -37,9 +37,9 @@ ifeq (,$(findstring PLATFORM_MEMORY_BANKS,$(CONFIGS)))
|
|||
endif
|
||||
ifeq (,$(findstring PLATFORM_MEMORY_ADDR_WIDTH,$(CONFIGS)))
|
||||
ifeq ($(XLEN),64)
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=41
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=47
|
||||
else
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=25
|
||||
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=31
|
||||
endif
|
||||
endif
|
||||
ifeq (,$(findstring PLATFORM_MEMORY_DATA_WIDTH,$(CONFIGS)))
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ module vortex_afu_shim #(
|
|||
parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
|
||||
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
|
||||
parameter C_M_AXI_MEM_ID_WIDTH = `PLATFORM_MEMORY_ID_WIDTH,
|
||||
parameter C_M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH + $clog2(`PLATFORM_MEMORY_DATA_WIDTH/8),
|
||||
parameter C_M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH,
|
||||
parameter C_M_AXI_MEM_DATA_WIDTH = `PLATFORM_MEMORY_DATA_WIDTH,
|
||||
parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_BANKS
|
||||
) (
|
||||
|
|
|
|||
|
|
@ -184,7 +184,7 @@ public:
|
|||
#endif
|
||||
|
||||
// calculate memory bank size
|
||||
mem_bank_size_ = ((1ull << PLATFORM_MEMORY_ADDR_WIDTH) / PLATFORM_MEMORY_BANKS) * PLATFORM_MEMORY_DATA_SIZE;
|
||||
mem_bank_size_ = 1ull << PLATFORM_MEMORY_ADDR_WIDTH;
|
||||
|
||||
// allocate RAM
|
||||
ram_ = new RAM(0, RAM_PAGE_SIZE);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue