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adding test coverage for xilinx synthesis

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This commit is contained in:
Blaise Tine 2024-08-22 02:51:17 -07:00
parent ca3499f3df
commit e4bfa47895
22 changed files with 415 additions and 18320 deletions
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119
hw/scripts/bin2coe.py
View file

@ -14,78 +14,83 @@
# limitations under the License.
import argparse
import os
g_memory = {}
def parse_binfile_option(option):
addr, path = option.split(':')
return int(addr, 0), path
def hex2bin(ch):
return int(ch, 16) if ch.isdigit() or ch in 'abcdefABCDEF' else 0
def parse_value_option(option):
addr, value = option.split(':')
return int(addr, 0), value
def process_binary(binfname, wordsize, binaddr):
with open(binfname, 'rb') as f:
buffer = list(f.read())
g_memory[binaddr] = buffer
return (len(buffer) + wordsize - 1) // wordsize
def load_binary_data(addr, path, word_size, memory, little_endian):
with open(path, 'rb') as f:
binary_data = f.read()
def process_data(datfname, wordsize):
offset, buffer = 0, []
with open(datfname, 'r') as f:
for line in f:
line = line.strip()
if line.startswith("#"):
continue
if line.startswith("@"):
if buffer:
g_memory[offset] = buffer
offset = int(line[1:], 16)
buffer = []
else:
for i in range(0, len(line), 2):
byte = hex2bin(line[i]) << 4 | hex2bin(line[i+1])
buffer.append(byte)
if len(buffer) % wordsize:
buffer.extend([0] * (wordsize - len(buffer) % wordsize))
offset += 1
if buffer:
g_memory[offset] = buffer
return offset
word_count = len(binary_data) // word_size
if len(binary_data) % word_size != 0:
word_count += 1
def write_coe(outfname, wordsize, depth, defval):
with open(outfname, 'w') as f:
f.write("MEMORY_INITIALIZATION_RADIX=16;\nMEMORY_INITIALIZATION_VECTOR=\n")
i = 0
for addr in sorted(g_memory):
while i < addr:
f.write(f"{defval},\n")
i += 1
data = g_memory[addr]
for j in range(0, len(data), wordsize):
f.write(",".join([f"{byte:02x}" for byte in data[j:j+wordsize][::-1]]) + ",\n")
i += 1
while i < depth:
f.write(f"{defval},\n")
i += 1
f.seek(f.tell() - 2, 0) # Remove the last comma
f.write(";\n")
for i in range(word_count):
word_data = binary_data[i * word_size: (i + 1) * word_size]
if little_endian:
word_data = word_data[::-1] # Reverse the byte order for little-endian
hex_value = word_data.hex().zfill(word_size * 2)
memory[addr + i] = hex_value
def add_value_data(addr, value, memory, word_size):
value = value.zfill(word_size * 2)
memory[addr] = value
def binary_to_coe(output_file, word_size, depth, default_value, memory):
if depth == 0:
depth = max(memory.keys()) + 1
with open(output_file, 'w') as coe_file:
coe_file.write("; This file was generated from binary blobs and/or values\n")
coe_file.write("memory_initialization_radix=16;\n")
coe_file.write("memory_initialization_vector=\n")
for addr in range(depth):
hex_value = memory.get(addr, default_value)
coe_file.write(f"{hex_value},\n")
coe_file.seek(coe_file.tell() - 2)
coe_file.write(";\n")
def main():
parser = argparse.ArgumentParser(description="Binary to Xilinx COE File Converter")
parser.add_argument("--binary", help="Input binary file.")
parser.add_argument("--data", help="Input data file.")
parser = argparse.ArgumentParser(description="Convert binaries and values to a Xilinx COE file.")
parser.add_argument("--binfile", action='append', help="Binary file with starting address in the format <addr>:<path>")
parser.add_argument("--value", action='append', help="Hex value with starting address in the format <addr>:<value>")
parser.add_argument("--out", default="output.coe", help="Output file (optional).")
parser.add_argument("--wordsize", type=int, default=4, help="Word size in bytes (default 4).")
parser.add_argument("--depth", type=int, default=0, help="Address size (optional).")
parser.add_argument("--binaddr", type=int, default=0, help="Binary address (optional).")
parser.add_argument("--default", default="00", help="Default hex value as string (optional).")
parser.add_argument("--little_endian", action='store_true', help="Interpret binary files as little-endian (default is big-endian).")
args = parser.parse_args()
depth = max(
process_binary(args.binary, args.wordsize, args.binaddr) if args.binary else 0,
process_data(args.data, args.wordsize) if args.data else 0,
args.depth
)
if args.binfile is None and args.value is None:
raise ValueError("At least one --binfile or --value must be provided.")
write_coe(args.out, args.wordsize, depth, args.default)
# Initialize memory dictionary
memory = {}
# Process binary files
if args.binfile:
for option in args.binfile:
addr, path = parse_binfile_option(option)
load_binary_data(addr, path, args.wordsize, memory, args.little_endian)
# Process individual values
if args.value:
for option in args.value:
addr, value = parse_value_option(option)
add_value_data(addr, value, memory, args.wordsize)
# Generate the COE file
binary_to_coe(args.out, args.wordsize, args.depth, args.default.zfill(args.wordsize * 2), memory)
if __name__ == "__main__":
main()

9
hw/syn/altera/dut/Makefile
View file

@ -9,7 +9,7 @@ SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
.PHONY: dogfood unittest pipeline mem_unit lmem cache fpu core issue vortex top test
.PHONY: dogfood unittest pipeline mem_unit lmem cache fpu core issue vortex top
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log:
@ -68,9 +68,4 @@ vortex: ip-gen
top: ip-gen
mkdir -p top/$(BUILD_DIR)
cp top/Makefile top/$(BUILD_DIR)
$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &
test: ip-gen
mkdir -p test/$(BUILD_DIR)
cp test/Makefile test/$(BUILD_DIR)
$(MAKE) -C test/$(BUILD_DIR) clean && $(MAKE) -C test/$(BUILD_DIR) > test/$(BUILD_DIR)/build.log 2>&1 &
$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &

3
hw/syn/altera/dut/common.mk
View file

@ -1,7 +1,7 @@
ROOT_DIR := $(realpath ../../../../../..)
include $(ROOT_DIR)/config.mk
SRC_DIR := $(VORTEX_HOME)/hw/syn/altera/quartus
SRC_DIR := $(VORTEX_HOME)/hw/syn/altera/dut
RTL_DIR := $(VORTEX_HOME)/hw/rtl
AFU_DIR := $(RTL_DIR)/afu/opae
@ -21,7 +21,6 @@ endif
CONFIGS += -DNDEBUG
CONFIGS += -DQUARTUS
CONFIGS += -DSYNTHESIS
CONFIGS += -DNOGLOBALS
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf

63
hw/syn/xilinx/dut/Makefile Normal file
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@ -0,0 +1,63 @@
ROOT_DIR := $(realpath ../../../..)
include $(ROOT_DIR)/config.mk
PREFIX ?= build
BUILD_DIR := $(PREFIX)
.PHONY: dogfood unittest pipeline mem_unit lmem cache fpu core issue vortex top
dogfood:
mkdir -p dogfood/$(BUILD_DIR)
cp dogfood/Makefile dogfood/$(BUILD_DIR)
$(MAKE) -C dogfood/$(BUILD_DIR) clean && $(MAKE) -C dogfood/$(BUILD_DIR) > dogfood/$(BUILD_DIR)/build.log 2>&1 &
unittest:
mkdir -p unittest/$(BUILD_DIR)
cp unittest/Makefile unittest/$(BUILD_DIR)
$(MAKE) -C unittest/$(BUILD_DIR) clean && $(MAKE) -C unittest/$(BUILD_DIR) > unittest/$(BUILD_DIR)/build.log 2>&1 &
pipeline:
mkdir -p pipeline/$(BUILD_DIR)
cp pipeline/Makefile pipeline/$(BUILD_DIR)
$(MAKE) -C pipeline/$(BUILD_DIR) clean && $(MAKE) -C pipeline/$(BUILD_DIR) > pipeline/$(BUILD_DIR)/build.log 2>&1 &
mem_unit:
mkdir -p mem_unit/$(BUILD_DIR)
cp mem_unit/Makefile mem_unit/$(BUILD_DIR)
$(MAKE) -C mem_unit/$(BUILD_DIR) clean && $(MAKE) -C mem_unit/$(BUILD_DIR) > mem_unit/$(BUILD_DIR)/build.log 2>&1 &
lmem:
mkdir -p lmem/$(BUILD_DIR)
cp lmem/Makefile lmem/$(BUILD_DIR)
$(MAKE) -C lmem/$(BUILD_DIR) clean && $(MAKE) -C lmem/$(BUILD_DIR) > lmem/$(BUILD_DIR)/build.log 2>&1 &
cache:
mkdir -p cache/$(BUILD_DIR)
cp cache/Makefile cache/$(BUILD_DIR)
$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
fpu:
mkdir -p fpu/$(BUILD_DIR)
cp fpu/Makefile fpu/$(BUILD_DIR)
$(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 &
core:
mkdir -p core/$(BUILD_DIR)
cp core/Makefile core/$(BUILD_DIR)
$(MAKE) -C core/$(BUILD_DIR) clean && $(MAKE) -C core/$(BUILD_DIR) > core/$(BUILD_DIR)/build.log 2>&1 &
issue:
mkdir -p issue/$(BUILD_DIR)
cp issue/Makefile issue/$(BUILD_DIR)
$(MAKE) -C issue/$(BUILD_DIR) clean && $(MAKE) -C issue/$(BUILD_DIR) > issue/$(BUILD_DIR)/build.log 2>&1 &
vortex:
mkdir -p vortex/$(BUILD_DIR)
cp vortex/Makefile vortex/$(BUILD_DIR)
$(MAKE) -C vortex/$(BUILD_DIR) clean && $(MAKE) -C vortex/$(BUILD_DIR) > vortex/$(BUILD_DIR)/build.log 2>&1 &
top:
mkdir -p top/$(BUILD_DIR)
cp top/Makefile top/$(BUILD_DIR)
$(MAKE) -C top/$(BUILD_DIR) clean && $(MAKE) -C top/$(BUILD_DIR) > top/$(BUILD_DIR)/build.log 2>&1 &

7
hw/syn/xilinx/dut/cache/Makefile vendored Normal file
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@ -0,0 +1,7 @@
PROJECT = VX_cache_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache

37
hw/syn/xilinx/dut/common.mk Normal file
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@ -0,0 +1,37 @@
ROOT_DIR := $(realpath ../../../../../..)
include $(ROOT_DIR)/config.mk
DEVICE ?= xcu55c-fsvh2892-2L-e
VIVADO := $(XILINX_VIVADO)/bin/vivado
SRC_DIR := $(VORTEX_HOME)/hw/syn/xilinx/dut
RTL_DIR := $(VORTEX_HOME)/hw/rtl
AFU_DIR := $(RTL_DIR)/afu/xrt
SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
CONFIGS += -DNDEBUG
CONFIGS += -DVIVADO
CONFIGS += -DSYNTHESIS
# Build targets
all: $(PROJECT).xpr
gen-sources: project_1/sources.txt
project_1/sources.txt:
mkdir -p project_1
$(SCRIPT_DIR)/gen_sources.sh $(CONFIGS) $(RTL_INCLUDE) -T$(TOP_LEVEL_ENTITY) -P -Cproject_1/src -Oproject_1/sources.txt
build: $(PROJECT).xpr
$(PROJECT).xpr: project_1/sources.txt
$(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR)
clean:
rm -rf project_1
rm -rf .Xil
rm -f *.rpt
rm -f vivado*.log
rm -f vivado*.jou
.PHONY: all gen-sources build clean

14
hw/syn/xilinx/dut/core/Makefile Normal file
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@ -0,0 +1,14 @@
PROJECT = VX_core_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
#CONFIGS += -DNUM_WARPS=32
#CONFIGS += -DNUM_THREADS=32
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

11
hw/syn/xilinx/dut/fpu/Makefile Normal file
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@ -0,0 +1,11 @@
PROJECT = VX_fpu_dsp
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)

14
hw/syn/xilinx/dut/issue/Makefile Normal file
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@ -0,0 +1,14 @@
PROJECT = VX_issue_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
#CONFIGS += -DNUM_WARPS=32
#CONFIGS += -DNUM_THREADS=32
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem $(FPU_INCLUDE) -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

7
hw/syn/xilinx/dut/lmem/Makefile Normal file
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@ -0,0 +1,7 @@
PROJECT = VX_local_mem_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem

7
hw/syn/xilinx/dut/mem_unit/Makefile Normal file
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@ -0,0 +1,7 @@
PROJECT = VX_mem_unit_top
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/mem -I$(RTL_DIR)/core -I$(RTL_DIR)/fpu

82
hw/syn/xilinx/dut/project.tcl Normal file
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@ -0,0 +1,82 @@
# Copyright © 2019-2023
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
if { $::argc != 5 } {
puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n"
puts "Usage: $::argv0 <top_module> <device_part> <vcs_file> <xdc_file> <tool_dir>\n"
exit
}
# Set the project name
set project_name "project_1"
set top_module [lindex $::argv 0]
set device_part [lindex $::argv 1]
set vcs_file [lindex $::argv 2]
set xdc_file [lindex $::argv 3]
set tool_dir [lindex $::argv 4]
#puts top_module
#puts $device_part
#puts $vcs_file
#puts xdc_file
#puts $tool_dir
source "${tool_dir}/parse_vcs_list.tcl"
set vlist [parse_vcs_list "${vcs_file}"]
set vsources_list [lindex $vlist 0]
set vincludes_list [lindex $vlist 1]
set vdefines_list [lindex $vlist 2]
#puts $vsources_list
#puts $vincludes_list
#puts $vdefines_list
# Create project
create_project $project_name $project_name -force -part $device_part
# Add constrains file
read_xdc $xdc_file
# Add the design sources
add_files -norecurse -verbose $vsources_list
# process defines
set obj [current_fileset]
foreach def $vdefines_list {
set_property verilog_define $def $obj
}
# Synthesis
synth_design -top $top_module -include_dirs $vincludes_list -flatten_hierarchy none
write_checkpoint -force post_synth.dcp
report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
# Optimize
opt_design
# Place
place_design
write_checkpoint -force post_place.dcp
report_place_status -file place.rpt
# Route
route_design
write_checkpoint -force post_route.dcp
report_route_status -file route.rpt
# Generate the synthesis report
report_timing -file timing.rpt
report_power -file power.rpt
report_drc -file drc.rpt

1
hw/syn/xilinx/dut/project.xdc Normal file
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@ -0,0 +1 @@
## empty

32
hw/syn/xilinx/dut/top/Makefile Normal file
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@ -0,0 +1,32 @@
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
# AFU parameters
CONFIGS += -DNOPAE
CONFIGS += -DPLATFORM_PROVIDES_LOCAL_MEMORY
ifeq (,$(findstring PLATFORM_PARAM_LOCAL_MEMORY_BANKS,$(CONFIGS)))
CONFIGS += -DPLATFORM_PARAM_LOCAL_MEMORY_BANKS=2
endif
ifeq (,$(findstring PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH,$(CONFIGS)))
CONFIGS += -DPLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH=26
endif
ifeq (,$(findstring PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH,$(CONFIGS)))
CONFIGS += -DPLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH=512
endif
ifeq (,$(findstring PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH,$(CONFIGS)))
CONFIGS += -DPLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH=4
endif
#CONFIGS += -DNUM_CORES=2
#CONFIGS += -DNUM_WARPS=32
#CONFIGS += -DNUM_THREADS=32
#CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

4
hw/syn/altera/dut/test/Makefile → hw/syn/xilinx/dut/unittest/Makefile
View file

@ -1,4 +1,4 @@
PROJECT = Vortex
PROJECT = Unittest
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
@ -8,4 +8,4 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

16
hw/syn/xilinx/dut/vortex/Makefile Normal file
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@ -0,0 +1,16 @@
PROJECT = Vortex
TOP_LEVEL_ENTITY = $(PROJECT)
SRC_FILE = $(PROJECT).sv
include ../../common.mk
#CONFIGS += -DNUM_CORES=2
#CONFIGS += -DNUM_WARPS=32
#CONFIGS += -DNUM_THREADS=32
#CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE)

24
hw/syn/xilinx/sandbox/Makefile
View file

@ -1,17 +1,22 @@
ROOT_DIR := $(realpath ../../../..)
include $(ROOT_DIR)/config.mk
DEVICE ?= xcu55c-fsvh2892-2L-e
VIVADO := $(XILINX_VIVADO)/bin/vivado
SRC_DIR := $(VORTEX_HOME)/hw/syn/xilinx/test
SRC_DIR := $(VORTEX_HOME)/hw/syn/xilinx/sandbox
RTL_DIR := $(VORTEX_HOME)/hw/rtl
DPI_DIR := $(VORTEX_HOME)/hw/dpi
AFU_DIR := $(RTL_DIR)/afu/opae
AFU_DIR := $(RTL_DIR)/afu/xrt
SCRIPT_DIR := $(VORTEX_HOME)/hw/scripts
KERNEL ?= fibonacci
COE_FILE := $(shell realpath kernel.bin.coe)
ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
@ -19,14 +24,13 @@ ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
endif
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
RTL_INCLUDE += $(FPU_INCLUDE)
RTL_INCLUDE += -I$(SRC_DIR)/project_1_files
RTL_INCLUDE += -I$(SRC_DIR)
# compilation flags
CFLAGS += -DNDEBUG -DSYNTHESIS -DVIVADO
CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)
CFLAGS += -DEXT_F_DISABLE
#CFLAGS += -DNUM_CORES 4
# update memory layout for 2MB RAM
CFLAGS += -DSTARTUP_ADDR=32\'h80000
@ -34,6 +38,9 @@ CFLAGS += -DSTACK_BASE_ADDR=32\'hFF000
all: build
project2.tcl: project.tcl
@sed -e "s/@COE_FILE@/$(ESCAPED_COE_FILE)/g" $< > $@
$(KERNEL).bin:
$(MAKE) -C $(ROOT_DIR)/kernel clean
STACK_BASE_ADDR=0xFF000 $(MAKE) -C $(ROOT_DIR)/kernel
@ -42,7 +49,7 @@ $(KERNEL).bin:
cp $(ROOT_DIR)/tests/kernel/$(KERNEL)/$(KERNEL).bin $(KERNEL).bin
kernel.bin.coe: $(KERNEL).bin
$(SCRIPT_DIR)/bin2coe.py --out=$@ --binary=$(KERNEL).bin --binaddr=8192 --depth=16384 --wordsize=64
$(SCRIPT_DIR)/bin2coe.py --out=$@ --binfile=8192:$(KERNEL).bin --depth=16384 --wordsize=64 --little_endian
gen-sources: project_1/sources.txt
project_1/sources.txt:
@ -50,11 +57,12 @@ project_1/sources.txt:
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt
build: project_1/project_1.xpr
project_1/project_1.xpr: project_1/sources.txt kernel.bin.coe project.tcl
$(VIVADO) -mode batch -source project.tcl -tclargs project_1/sources.txt project_1/src $(SCRIPT_DIR)
project_1/project_1.xpr: project_1/sources.txt kernel.bin.coe project2.tcl
$(VIVADO) -mode batch -source project2.tcl -tclargs $(DEVICE) project_1/sources.txt $(SCRIPT_DIR)
run: project_1/project_1.xpr
$(VIVADO) project_1/project_1.xpr &
clean:
rm -rf project_1 $(KERNEL).bin kernel.bin.coe
rm -rf project_1 project2.tcl $(KERNEL).bin kernel.bin.coe
rm -rf .Xil *.log *.jou

0
hw/syn/xilinx/sandbox/project_1_files/Vortex_top.v → hw/syn/xilinx/sandbox/Vortex_top.v
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0
hw/syn/xilinx/sandbox/project_1_files/Vortex_wrap.sv → hw/syn/xilinx/sandbox/Vortex_wrap.sv
View file

1899
hw/syn/xilinx/sandbox/project.tcl.in
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File diff suppressed because it is too large Load diff

16386
hw/syn/xilinx/sandbox/project_1_files/kernel.bin.coe
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File diff suppressed because it is too large Load diff

0
hw/syn/xilinx/sandbox/project_1_files/testbench.v → hw/syn/xilinx/sandbox/testbench.v
View file