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Parameterization working

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This commit is contained in:
Savan Roshan 2019-11-07 00:14:46 -05:00
parent 9e2de897f0
commit e4ee2a9cbd
10 changed files with 565 additions and 493 deletions
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20
rtl/VX_define.v
View file

@ -123,8 +123,10 @@
`endif
`define DCACHE_BLOCK 128 //Bytes
`define DCACHE_BANKS 8
`define DCACHE_LOG_NUM_BANKS $clog2(`DCACHE_BANKS)
`define DCACHE_NUM_WORDS_PER_BLOCK 4
`define DCACHE_NUM_REQ `NT
`define DCACHE_LOG_NUM_REQ $clog2(`DCACHE_NUM_REQ)
`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
//`define DCACHE_WAY_INDEX 1
@ -133,28 +135,36 @@
// Offset
`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK))
`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_BANKS))
`define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)
`define DCACHE_ADDR_OFFSET_ST (2+$clog2(`DCACHE_BANKS))
`define DCACHE_ADDR_OFFSET_ED (`DCACHE_ADDR_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)
`define DCACHE_ADDR_OFFSET_RNG `DCACHE_OFFSET_ED:`DCACHE_OFFSET_ST
`define DCACHE_ADDR_OFFSET_RNG `DCACHE_ADDR_OFFSET_ED:`DCACHE_ADDR_OFFSET_ST
`define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0
`define DCACHE_OFFSET_ST 0
`define DCACHE_OFFSET_ED ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1)
// Index
`define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK))
`define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND))
`define DCACHE_IND_ST (`DCACHE_OFFSET_ED+1)
`define DCACHE_IND_ST (`DCACHE_ADDR_OFFSET_ED+1)
`define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1)
`define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST
`define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0
`define DCACHE_IND_SIZE_START 0
`define DCACHE_IND_SIZE_END `DCACHE_IND_NB-1
// Tag
`define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1)
`define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0
`define DCACHE_TAG_SIZE_START 0
`define DCACHE_TAG_SIZE_END (32-(`DCACHE_IND_ED+1)-1)
`define DCACHE_ADDR_TAG_START (`DCACHE_IND_ED+1)
`define DCACHE_ADDR_TAG_END 31

37
rtl/VX_dmem_controller.v
View file

@ -51,18 +51,31 @@ module VX_dmem_controller (
);
VX_d_cache
/*#(
.CACHE_SIZE(4096), // Bytes
`ifdef SYN
.CACHE_WAYS(1),
`else
.CACHE_WAYS(2),
`endif
.CACHE_BLOCK(128), // Bytes
.CACHE_BANKS(8),
.NUM_REQ(`NT)
)*/ dcache
VX_d_cache#(
.CACHE_SIZE (`DCACHE_SIZE),
.CACHE_WAYS (`DCACHE_WAYS),
.CACHE_BLOCK (`DCACHE_BLOCK),
.CACHE_BANKS (`DCACHE_BANKS),
.LOG_NUM_BANKS (`DCACHE_LOG_NUM_BANKS),
.NUM_REQ (`DCACHE_NUM_REQ),
.LOG_NUM_REQ (`DCACHE_LOG_NUM_REQ),
.NUM_IND (`DCACHE_NUM_IND),
.CACHE_WAY_INDEX (`DCACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK (`DCACHE_NUM_WORDS_PER_BLOCK),
.OFFSET_SIZE_START (`DCACHE_OFFSET_ST),
.OFFSET_SIZE_END (`DCACHE_OFFSET_ED),
.TAG_SIZE_START (`DCACHE_TAG_SIZE_START),
.TAG_SIZE_END (`DCACHE_TAG_SIZE_END),
.IND_SIZE_START (`DCACHE_IND_SIZE_START),
.IND_SIZE_END (`DCACHE_IND_SIZE_END),
.ADDR_TAG_START (`DCACHE_ADDR_TAG_START),
.ADDR_TAG_END (`DCACHE_ADDR_TAG_END),
.ADDR_OFFSET_START (`DCACHE_ADDR_OFFSET_ST),
.ADDR_OFFSET_END (`DCACHE_ADDR_OFFSET_ED),
.ADDR_IND_START (`DCACHE_IND_ST),
.ADDR_IND_END (`DCACHE_IND_ED)
)
dcache
(
.clk (clk),
.rst (reset),

324
rtl/Vortex.v
View file

@ -1,161 +1,163 @@
`include "../VX_define.v"
module Vortex
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 2,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)*/
(
input wire clk,
input wire reset,
input wire[31:0] icache_response_instruction,
output wire[31:0] icache_request_pc_address,
// IO
output wire io_valid,
output wire[31:0] io_data,
// Req
output reg [31:0] o_m_read_addr,
output reg [31:0] o_m_evict_addr,
output reg o_m_valid,
output reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output reg o_m_read_or_write,
// Rsp
input wire [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input wire i_m_ready,
output wire out_ebreak
);
wire memory_delay;
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_dcache_response_inter VX_dcache_rsp();
VX_dcache_request_inter VX_dcache_req();
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
VX_dram_req_rsp_inter VX_dram_req_rsp();
assign o_m_read_addr = VX_dram_req_rsp.o_m_read_addr;
assign o_m_evict_addr = VX_dram_req_rsp.o_m_evict_addr;
assign o_m_valid = VX_dram_req_rsp.o_m_valid;
assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
assign VX_dram_req_rsp.i_m_ready = i_m_ready;
genvar curr_bank;
genvar curr_word;
for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
end
end
// Icache Interface
VX_icache_response_inter icache_response_fe();
VX_icache_request_inter icache_request_fe();
assign icache_response_fe.instruction = icache_response_instruction;
assign icache_request_pc_address = icache_request_fe.pc_address;
/////////////////////////////////////////////////////////////////////////
// Front-end to Back-end
VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
// CSR Buses
// VX_csr_write_request_inter VX_csr_w_req();
VX_warp_ctl_inter VX_warp_ctl();
VX_front_end vx_front_end(
.clk (clk),
.reset (reset),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.schedule_delay (schedule_delay),
.icache_response_fe (icache_response_fe),
.icache_request_fe (icache_request_fe),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.fetch_ebreak (out_ebreak)
);
VX_scheduler schedule(
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.gpr_stage_delay (gpr_stage_delay),
.VX_bckE_req (VX_bckE_req),
.VX_writeback_inter(VX_writeback_inter),
.schedule_delay (schedule_delay)
);
VX_back_end vx_back_end(
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.VX_dcache_rsp (VX_dcache_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_writeback_inter (VX_writeback_inter),
.out_mem_delay (memory_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_controller VX_dmem_controller(
.clk (clk),
.reset (reset),
.VX_dram_req_rsp(VX_dram_req_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_dcache_rsp (VX_dcache_rsp)
);
// VX_csr_handler vx_csr_handler(
// .clk (clk),
// .in_decode_csr_address(decode_csr_address),
// .VX_csr_w_req (VX_csr_w_req),
// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data)
// );
endmodule // Vortex
`include "../VX_define.v"
module Vortex
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 2,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)*/
(
input wire clk,
input wire reset,
input wire[31:0] icache_response_instruction,
output wire[31:0] icache_request_pc_address,
// IO
output wire io_valid,
output wire[31:0] io_data,
// Req
output reg [31:0] o_m_read_addr,
output reg [31:0] o_m_evict_addr,
output reg o_m_valid,
output reg [31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output reg o_m_read_or_write,
// Rsp
input wire [31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input wire i_m_ready,
output wire out_ebreak
);
wire memory_delay;
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_dcache_response_inter VX_dcache_rsp();
VX_dcache_request_inter VX_dcache_req();
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
VX_dram_req_rsp_inter #(
.NUMBER_BANKS(`DCACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)) VX_dram_req_rsp();
assign o_m_read_addr = VX_dram_req_rsp.o_m_read_addr;
assign o_m_evict_addr = VX_dram_req_rsp.o_m_evict_addr;
assign o_m_valid = VX_dram_req_rsp.o_m_valid;
assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
assign VX_dram_req_rsp.i_m_ready = i_m_ready;
genvar curr_bank;
genvar curr_word;
for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
end
end
// Icache Interface
VX_icache_response_inter icache_response_fe();
VX_icache_request_inter icache_request_fe();
assign icache_response_fe.instruction = icache_response_instruction;
assign icache_request_pc_address = icache_request_fe.pc_address;
/////////////////////////////////////////////////////////////////////////
// Front-end to Back-end
VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
// CSR Buses
// VX_csr_write_request_inter VX_csr_w_req();
VX_warp_ctl_inter VX_warp_ctl();
VX_front_end vx_front_end(
.clk (clk),
.reset (reset),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.schedule_delay (schedule_delay),
.icache_response_fe (icache_response_fe),
.icache_request_fe (icache_request_fe),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.fetch_ebreak (out_ebreak)
);
VX_scheduler schedule(
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.gpr_stage_delay (gpr_stage_delay),
.VX_bckE_req (VX_bckE_req),
.VX_writeback_inter(VX_writeback_inter),
.schedule_delay (schedule_delay)
);
VX_back_end vx_back_end(
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.VX_warp_ctl (VX_warp_ctl),
.VX_bckE_req (VX_bckE_req),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.VX_dcache_rsp (VX_dcache_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_writeback_inter (VX_writeback_inter),
.out_mem_delay (memory_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_controller VX_dmem_controller(
.clk (clk),
.reset (reset),
.VX_dram_req_rsp(VX_dram_req_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_dcache_rsp (VX_dcache_rsp)
);
// VX_csr_handler vx_csr_handler(
// .clk (clk),
// .in_decode_csr_address(decode_csr_address),
// .VX_csr_w_req (VX_csr_w_req),
// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data)
// );
endmodule // Vortex

96
rtl/cache/VX_Cache_Bank.v vendored
View file

@ -7,12 +7,30 @@
module VX_Cache_Bank
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8
)*/
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 8,
parameter LOG_NUM_REQ = 3,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter OFFSET_SIZE_START = 0,
parameter OFFSET_SIZE_END = 1,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7,
parameter ADDR_TAG_START = 15,
parameter ADDR_TAG_END = 31,
parameter ADDR_OFFSET_START = 5,
parameter ADDR_OFFSET_END = 6,
parameter ADDR_IND_START = 7,
parameter ADDR_IND_END = 14
)
(
clk,
rst,
@ -58,25 +76,25 @@ module VX_Cache_Bank
//input wire write_from_mem;
// Reading Data
input wire[`DCACHE_IND_SIZE_RNG] actual_index;
input wire[IND_SIZE_END:IND_SIZE_START] actual_index;
input wire[`DCACHE_TAG_SIZE_RNG] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[`DCACHE_OFFSET_SIZE_RNG] block_offset;
input wire[TAG_SIZE_END:TAG_SIZE_START] o_tag; // When write_from_mem = 1, o_tag is the new tag
input wire[OFFSET_SIZE_END:OFFSET_SIZE_START] block_offset;
input wire[31:0] writedata;
input wire valid_in;
input wire read_or_write; // Specifies if it is a read or write operation
input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
input wire[2:0] i_p_mem_read;
input wire[2:0] i_p_mem_write;
input wire[1:0] byte_select;
input wire[`DCACHE_WAY_INDEX-1:0] evicted_way;
output wire[`DCACHE_WAY_INDEX-1:0] way_use;
input wire[CACHE_WAY_INDEX-1:0] evicted_way;
output wire[CACHE_WAY_INDEX-1:0] way_use;
// Outputs
// Normal shit
@ -89,13 +107,13 @@ module VX_Cache_Bank
output wire[31:0] eviction_addr; // What's the eviction tag
// Eviction Data (Extraction)
output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[`DCACHE_TAG_SIZE_RNG] tag_use;
wire[`DCACHE_TAG_SIZE_RNG] eviction_tag;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
wire[TAG_SIZE_END:TAG_SIZE_START] tag_use;
wire[TAG_SIZE_END:TAG_SIZE_START] eviction_tag;
wire valid_use;
wire dirty_use;
wire access;
@ -104,8 +122,8 @@ module VX_Cache_Bank
wire[`DCACHE_WAY_INDEX-1:0] update_way;
wire[`DCACHE_WAY_INDEX-1:0] way_to_update;
wire[CACHE_WAY_INDEX-1:0] update_way;
wire[CACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in;
@ -181,10 +199,10 @@ module VX_Cache_Bank
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < `DCACHE_NUM_WORDS_PER_BLOCK; g = g + 1) begin
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 :
@ -200,13 +218,15 @@ module VX_Cache_Bank
end
/*VX_cache_data_per_index #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS),
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(*/
VX_cache_data_per_index data_structures(
VX_cache_data_per_index #(
.CACHE_WAYS (CACHE_WAYS),
.NUM_IND (NUM_IND),
.CACHE_WAY_INDEX (CACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END)) data_structures(
.clk (clk),
.rst (rst),
.valid_in (valid_in),
@ -225,26 +245,6 @@ module VX_Cache_Bank
.way (way_use)
);
// VX_cache_data #(
// .CACHE_SIZE(CACHE_SIZE),
// .CACHE_WAYS(CACHE_WAYS),
// .CACHE_BLOCK(CACHE_BLOCK),
// .CACHE_BANKS(CACHE_BANKS),
// .NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(
// .clk (clk),
// .rst (rst),
// // Inputs
// .addr (actual_index),
// .we (we),
// .evict (write_from_mem),
// .data_write(data_write),
// .tag_write (o_tag),
// // Outputs
// .tag_use (tag_use),
// .data_use (data_use),
// .valid_use (valid_use),
// .dirty_use (dirty_use)
// );
endmodule

50
rtl/cache/VX_cache_bank_valid.v vendored
View file

@ -1,24 +1,26 @@
`include "../VX_define.v"
module VX_cache_bank_valid
#(
parameter NUMBER_BANKS = 0
)
(
input wire [`NT_M1:0] i_p_valid,
input wire [`NT_M1:0][31:0] i_p_addr,
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
generate
integer t_id;
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][2+$clog2(NUMBER_BANKS)-1:2]][t_id] = i_p_valid[t_id];
end
end
endgenerate
endmodule
`include "../VX_define.v"
module VX_cache_bank_valid
#(
parameter NUMBER_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 1
)
(
input wire [NUM_REQ-1:0] i_p_valid,
input wire [NUM_REQ-1:0][31:0] i_p_addr,
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
generate
integer t_id;
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id < NUM_REQ; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][2+LOG_NUM_BANKS-1:2]][t_id] = i_p_valid[t_id];
end
end
endgenerate
endmodule

49
rtl/cache/VX_cache_data.v vendored
View file

@ -3,29 +3,30 @@
`include "../VX_define.v"
module VX_cache_data
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4
)*/
#(
parameter NUM_IND = 8,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7
)
(
input wire clk, rst, // Clock
// `ifdef PARAM
// Addr
input wire[`DCACHE_IND_SIZE_RNG] addr,
input wire[IND_SIZE_END:IND_SIZE_START] addr,
// WE
input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
// Data
input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[`DCACHE_TAG_SIZE_RNG] tag_write,
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write,
output wire[`DCACHE_TAG_SIZE_RNG] tag_use,
output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use
// `else
@ -50,7 +51,7 @@ module VX_cache_data
//localparam NUMBER_BANKS = CACHE_BANKS;
//localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS);
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
//localparam NUMBER_INDEXES = NUM_IND;
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
@ -61,10 +62,10 @@ module VX_cache_data
`ifndef SYN
// (3:0) 4 bytes
reg[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[`DCACHE_NUM_IND-1:0]; // Actual Data
reg[`DCACHE_TAG_SIZE_RNG] tag[`DCACHE_NUM_IND-1:0];
reg valid[`DCACHE_NUM_IND-1:0];
reg dirty[`DCACHE_NUM_IND-1:0];
reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUM_IND-1:0]; // Actual Data
reg[TAG_SIZE_END:TAG_SIZE_START] tag[NUM_IND-1:0];
reg valid[NUM_IND-1:0];
reg dirty[NUM_IND-1:0];
// 16 bytes
@ -77,7 +78,7 @@ module VX_cache_data
integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < `DCACHE_NUM_IND; ini_ind=ini_ind+1) begin
for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin
data[ini_ind] <= 0;
tag[ini_ind] <= 0;
valid[ini_ind] <= 0;
@ -88,7 +89,7 @@ module VX_cache_data
if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1;
for (f = 0; f < `DCACHE_NUM_WORDS_PER_BLOCK; f = f + 1) begin
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
@ -103,11 +104,11 @@ module VX_cache_data
wire cena = 1;
wire cenb_d = (|we);
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b;
for (cur_b = 0; cur_b < `DCACHE_NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
for (cur_b = 0; cur_b < NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end
assign data_use = data_out_d;

78
rtl/cache/VX_cache_data_per_index.v vendored
View file

@ -3,33 +3,36 @@
`include "../VX_define.v"
module VX_cache_data_per_index
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4)
)*/
#(
parameter CACHE_WAYS = 1,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7
)
(
input wire clk, // Clock
input wire rst,
input wire valid_in,
// Addr
input wire[`DCACHE_IND_SIZE_RNG] addr,
input wire[IND_SIZE_END:IND_SIZE_START] addr,
// WE
input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
input wire evict,
input wire[`DCACHE_WAY_INDEX-1:0] way_to_update,
input wire[CACHE_WAY_INDEX-1:0] way_to_update,
// Data
input wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[`DCACHE_TAG_SIZE_RNG] tag_write,
input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
input wire[TAG_SIZE_END:TAG_SIZE_START] tag_write,
output wire[`DCACHE_TAG_SIZE_RNG] tag_use,
output wire[`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use,
output wire[`DCACHE_WAY_INDEX-1:0] way
output wire[CACHE_WAY_INDEX-1:0] way
);
//localparam NUMBER_BANKS = CACHE_BANKS;
@ -37,30 +40,30 @@ module VX_cache_data_per_index
// localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4);
//localparam NUMBER_INDEXES = `DCACHE_NUM_IND;
wire [`DCACHE_WAYS-1:0][`DCACHE_TAG_SIZE_RNG] tag_use_per_way;
wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [`DCACHE_WAYS-1:0] valid_use_per_way;
wire [`DCACHE_WAYS-1:0] dirty_use_per_way;
wire [`DCACHE_WAYS-1:0] hit_per_way;
reg [`DCACHE_NUM_IND-1:0][`DCACHE_WAY_INDEX-1:0] eviction_way_index;
wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [`DCACHE_WAYS-1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [`DCACHE_WAYS-1:0] write_from_mem_per_way;
wire [CACHE_WAYS-1:0][TAG_SIZE_END:TAG_SIZE_START] tag_use_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way;
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
reg [NUM_IND-1:0][CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
wire invalid_found;
wire [`DCACHE_WAY_INDEX-1:0] way_index;
wire [`DCACHE_WAY_INDEX-1:0] invalid_index;
wire [CACHE_WAY_INDEX-1:0] way_index;
wire [CACHE_WAY_INDEX-1:0] invalid_index;
if(`DCACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) valid_index
if(CACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
(
.valids(~valid_use_per_way),
.index (invalid_index),
.found (invalid_found)
);
VX_generic_priority_encoder #(.N(`DCACHE_WAYS)) way_indexing
VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing
(
.valids(hit_per_way),
.index (way_index),
@ -90,19 +93,20 @@ module VX_cache_data_per_index
genvar ways;
for(ways=0; ways < `DCACHE_WAYS; ways = ways + 1) begin
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0;
assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0;
/*VX_cache_data #(
.CACHE_SIZE(`CACHE_SIZE),
.CACHE_WAYS(`DCACHE_WAYS),
.CACHE_BLOCK(`CACHE_BLOCK),
.CACHE_BANKS(`CACHE_BANKS)) data_structures(*/
VX_cache_data data_structures(
VX_cache_data #(
.NUM_IND (NUM_IND),
.NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END)) data_structures(
.clk (clk),
.rst (rst),
// Inputs
@ -124,7 +128,7 @@ module VX_cache_data_per_index
eviction_way_index <= 0;
end else begin
if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries
if((eviction_way_index[addr]+1) == `DCACHE_WAYS) begin
if((eviction_way_index[addr]+1) == CACHE_WAYS) begin
eviction_way_index[addr] <= 0;
end else begin
eviction_way_index[addr] <= (eviction_way_index[addr] + 1);

152
rtl/cache/VX_d_cache.v vendored
View file

@ -14,13 +14,30 @@
//`include "cache_set.v"
module VX_d_cache
/*#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter NUM_REQ = 8
)*/
#(
parameter CACHE_SIZE = 4096, // Bytes
parameter CACHE_WAYS = 1,
parameter CACHE_BLOCK = 128, // Bytes
parameter CACHE_BANKS = 8,
parameter LOG_NUM_BANKS = 3,
parameter NUM_REQ = 8,
parameter LOG_NUM_REQ = 3,
parameter NUM_IND = 8,
parameter CACHE_WAY_INDEX = 1,
parameter NUM_WORDS_PER_BLOCK = 4,
parameter OFFSET_SIZE_START = 0,
parameter OFFSET_SIZE_END = 1,
parameter TAG_SIZE_START = 0,
parameter TAG_SIZE_END = 16,
parameter IND_SIZE_START = 0,
parameter IND_SIZE_END = 7,
parameter ADDR_TAG_START = 15,
parameter ADDR_TAG_END = 31,
parameter ADDR_OFFSET_START = 5,
parameter ADDR_OFFSET_END = 6,
parameter ADDR_IND_START = 7,
parameter ADDR_IND_END = 14
)
(
clk,
rst,
@ -59,18 +76,18 @@ module VX_d_cache
//parameter cache_entry = 9;
input wire clk, rst;
input wire [`DCACHE_NUM_REQ-1:0] i_p_valid;
input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [`DCACHE_NUM_REQ-1:0][31:0] i_p_writedata;
input wire [NUM_REQ-1:0] i_p_valid;
input wire [NUM_REQ-1:0][31:0] i_p_addr; // FIXME
input wire [NUM_REQ-1:0][31:0] i_p_writedata;
input wire i_p_read_or_write; //, i_p_write;
output reg [`DCACHE_NUM_REQ-1:0][31:0] o_p_readdata;
output reg [NUM_REQ-1:0][31:0] o_p_readdata;
output wire o_p_delay;
output reg [31:0] o_m_evict_addr; // Address is xxxxxxxxxxoooobbbyy
output reg [31:0] o_m_read_addr;
output reg o_m_valid;
output reg[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
output reg o_m_read_or_write; //, o_m_write;
input wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
input wire i_m_ready;
input wire[2:0] i_p_mem_read;
@ -78,41 +95,41 @@ module VX_d_cache
// Buffer for final data
reg [`DCACHE_NUM_REQ-1:0][31:0] final_data_read;
reg [`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read;
wire[`DCACHE_NUM_REQ-1:0][31:0] new_final_data_read_Qual;
reg [NUM_REQ-1:0][31:0] final_data_read;
reg [NUM_REQ-1:0][31:0] new_final_data_read;
wire[NUM_REQ-1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = new_final_data_read_Qual;
wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] index_per_bank; // Index of thread each bank will try to service
wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[`DCACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[`DCACHE_BANKS - 1 : 0][`DCACHE_NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] index_per_bank; // Index of thread each bank will try to service
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] use_mask_per_bank; // A mask of index_per_bank
wire[CACHE_BANKS - 1 : 0] valid_per_bank; // Valid request going to each bank
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] threads_serviced_per_bank; // Bank successfully serviced per bank
wire[`DCACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[`DCACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[`DCACHE_BANKS-1:0] eviction_wb;
reg[`DCACHE_BANKS-1:0] eviction_wb_old;
wire[CACHE_BANKS-1:0][31:0] readdata_per_bank; // Data read from each bank
wire[CACHE_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss
wire[CACHE_BANKS-1:0] eviction_wb;
reg[CACHE_BANKS-1:0] eviction_wb_old;
wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_new;
reg [`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] evicted_way_old;
wire[`DCACHE_BANKS -1 : 0][`DCACHE_WAY_INDEX-1:0] way_used;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
wire[3:0] new_state;
wire[`DCACHE_NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[`DCACHE_NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[`DCACHE_NUM_REQ-1:0] new_stored_valid; // New stored valid
wire[NUM_REQ-1:0] use_valid; // Valid used throught the code
reg[NUM_REQ-1:0] stored_valid; // Saving the threads still left (bank conflict or bank miss)
wire[NUM_REQ-1:0] new_stored_valid; // New stored valid
reg[`DCACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
reg[31:0] evict_addr;
@ -127,39 +144,41 @@ module VX_d_cache
VX_cache_bank_valid #(.NUMBER_BANKS(`DCACHE_BANKS)) multip_banks(
VX_cache_bank_valid #(.NUMBER_BANKS (CACHE_BANKS),
.LOG_NUM_BANKS (LOG_NUM_BANKS),
.NUM_REQ (NUM_REQ)) multip_banks(
.i_p_valid (use_valid),
.i_p_addr (i_p_addr),
.thread_track_banks(thread_track_banks)
);
reg[`DCACHE_NUM_REQ-1:0] threads_serviced_Qual;
reg[NUM_REQ-1:0] threads_serviced_Qual;
reg[`DCACHE_NUM_REQ-1:0] debug_hit_per_bank_mask[`DCACHE_BANKS-1:0];
reg[NUM_REQ-1:0] debug_hit_per_bank_mask[CACHE_BANKS-1:0];
genvar bid;
for (bid = 0; bid < `DCACHE_BANKS; bid=bid+1)
for (bid = 0; bid < CACHE_BANKS; bid=bid+1)
begin
wire[`DCACHE_NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`DCACHE_NUM_REQ)-1:0] use_thread_index = index_per_bank[bid];
wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[LOG_NUM_REQ-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(`DCACHE_NUM_REQ)) choose_thread(
VX_priority_encoder_w_mask #(.N(NUM_REQ)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
.index (index_per_bank[bid]),
.found (valid_per_bank[bid])
);
assign debug_hit_per_bank_mask[bid] = {`DCACHE_NUM_REQ{hit_per_bank[bid]}};
assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
integer test_bid;
always @(*) begin
new_final_data_read = 0;
for (test_bid=0; test_bid < `DCACHE_BANKS; test_bid=test_bid+1)
for (test_bid=0; test_bid < CACHE_BANKS; test_bid=test_bid+1)
begin
if (hit_per_bank[test_bid]) begin
new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
@ -168,7 +187,7 @@ module VX_d_cache
end
wire[`DCACHE_BANKS - 1 : 0] detect_bank_miss;
wire[CACHE_BANKS - 1 : 0] detect_bank_miss;
//assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
// threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
// threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
@ -176,7 +195,7 @@ module VX_d_cache
integer bbid;
always @(*) begin
threads_serviced_Qual = 0;
for (bbid = 0; bbid < `DCACHE_BANKS; bbid=bbid+1)
for (bbid = 0; bbid < CACHE_BANKS; bbid=bbid+1)
begin
threads_serviced_Qual = threads_serviced_Qual | threads_serviced_per_bank[bbid];
end
@ -185,7 +204,7 @@ module VX_d_cache
genvar tid;
for (tid = 0; tid < `DCACHE_NUM_REQ; tid =tid+1)
for (tid = 0; tid < NUM_REQ; tid =tid+1)
begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
@ -198,12 +217,12 @@ module VX_d_cache
assign o_p_delay = delay;
wire[`DCACHE_BANKS - 1 : 0][$clog2(`DCACHE_NUM_REQ)-1:0] send_index_to_bank = index_per_bank;
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] send_index_to_bank = index_per_bank;
wire[$clog2(`DCACHE_BANKS)-1:0] miss_bank_index;
wire[LOG_NUM_BANKS-1:0] miss_bank_index;
wire miss_found;
VX_generic_priority_encoder #(.N(`DCACHE_BANKS)) get_miss_index
VX_generic_priority_encoder #(.N(CACHE_BANKS)) get_miss_index
(
.valids(detect_bank_miss),
.index (miss_bank_index),
@ -259,7 +278,7 @@ module VX_d_cache
genvar bank_id;
generate
for (bank_id = 0; bank_id < `DCACHE_BANKS; bank_id = bank_id + 1)
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1)
begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
@ -270,9 +289,9 @@ module VX_d_cache
0;
wire[1:0] byte_select = bank_addr[1:0];
wire[`DCACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`DCACHE_ADDR_OFFSET_RNG];
wire[`DCACHE_IND_SIZE_RNG] cache_index = bank_addr[`DCACHE_ADDR_IND_RNG];
wire[`DCACHE_TAG_SIZE_RNG] cache_tag = bank_addr[`DCACHE_ADDR_TAG_RNG];
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START];
wire[IND_SIZE_END:IND_SIZE_START] cache_index = bank_addr[ADDR_IND_END:ADDR_IND_START];
wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START];
wire normal_valid_in = valid_per_bank[bank_id];
@ -281,12 +300,31 @@ module VX_d_cache
((state == SEND_MEM_REQ)) ? 1'b0 :
normal_valid_in;
/*VX_Cache_Bank #(
.CACHE_SIZE(CACHE_SIZE),
.CACHE_WAYS(CACHE_WAYS),
.CACHE_BLOCK(CACHE_BLOCK),
.CACHE_BANKS(CACHE_BANKS)) bank_structure*/
VX_Cache_Bank bank_structure(
VX_Cache_Bank #(
.CACHE_SIZE (CACHE_SIZE),
.CACHE_WAYS (CACHE_WAYS),
.CACHE_BLOCK (CACHE_BLOCK),
.CACHE_BANKS (CACHE_BANKS),
.LOG_NUM_BANKS (LOG_NUM_BANKS),
.NUM_REQ (NUM_REQ),
.LOG_NUM_REQ (LOG_NUM_REQ),
.NUM_IND (NUM_IND),
.CACHE_WAY_INDEX (CACHE_WAY_INDEX),
.NUM_WORDS_PER_BLOCK (NUM_WORDS_PER_BLOCK),
.OFFSET_SIZE_START (OFFSET_SIZE_START),
.OFFSET_SIZE_END (OFFSET_SIZE_END),
.TAG_SIZE_START (TAG_SIZE_START),
.TAG_SIZE_END (TAG_SIZE_END),
.IND_SIZE_START (IND_SIZE_START),
.IND_SIZE_END (IND_SIZE_END),
.ADDR_TAG_START (ADDR_TAG_START),
.ADDR_TAG_END (ADDR_TAG_END),
.ADDR_OFFSET_START (ADDR_OFFSET_START),
.ADDR_OFFSET_END (ADDR_OFFSET_END),
.ADDR_IND_START (ADDR_IND_START),
.ADDR_IND_END (ADDR_IND_END)
) bank_structure (
.clk (clk),
.rst (rst),
.state (state),

52
rtl/interfaces/VX_dram_req_rsp_inter.v
View file

@ -1,25 +1,27 @@
`include "../VX_define.v"
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
interface VX_dram_req_rsp_inter ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif
`include "../VX_define.v"
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
interface VX_dram_req_rsp_inter #(
parameter NUMBER_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif

200
rtl/simulate/VX_define.h
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@ -1,100 +1,100 @@
#define NT 4
#define NT_M1 (NT-1)
#define NW 8
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3
#define ALU_INST 19
#define S_INST 35
#define B_INST 99
#define LUI_INST 55
#define AUIPC_INST 23
#define JAL_INST 111
#define JALR_INST 103
#define SYS_INST 115
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
#define RS2_IMMED 1
#define RS2_REG 0
#define NO_MEM_READ 7
#define LB_MEM_READ 0
#define LH_MEM_READ 1
#define LW_MEM_READ 2
#define LBU_MEM_READ 4
#define LHU_MEM_READ 5
#define NO_MEM_WRITE 7
#define SB_MEM_WRITE 0
#define SH_MEM_WRITE 1
#define SW_MEM_WRITE 2
#define NO_BRANCH 0
#define BEQ 1
#define BNE 2
#define BLT 3
#define BGT 4
#define BLTU 5
#define BGTU 6
#define NO_ALU 15
#define ADD 0
#define SUB 1
#define SLLA 2
#define SLT 3
#define SLTU 4
#define XOR 5
#define SRL 6
#define SRA 7
#define OR 8
#define AND 9
#define SUBU 10
#define LUI_ALU 11
#define AUIPC_ALU 12
#define CSR_ALU_RW 13
#define CSR_ALU_RS 14
#define CSR_ALU_RC 15
// WRITEBACK
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
// JAL
#define JUMP 1
#define NO_JUMP 0
// STALLS
#define STALL 1
#define NO_STALL 0
#define TAKEN 1
#define NOT_TAKEN 0
#define ZERO_REG 0
// COLORS
#define GREEN "\033[32m"
#define RED "\033[31m"
#define DEFAULT "\033[39m"
#define NT 4
#define NT_M1 (NT-1)
#define NW 8
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3
#define ALU_INST 19
#define S_INST 35
#define B_INST 99
#define LUI_INST 55
#define AUIPC_INST 23
#define JAL_INST 111
#define JALR_INST 103
#define SYS_INST 115
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
#define RS2_IMMED 1
#define RS2_REG 0
#define NO_MEM_READ 7
#define LB_MEM_READ 0
#define LH_MEM_READ 1
#define LW_MEM_READ 2
#define LBU_MEM_READ 4
#define LHU_MEM_READ 5
#define NO_MEM_WRITE 7
#define SB_MEM_WRITE 0
#define SH_MEM_WRITE 1
#define SW_MEM_WRITE 2
#define NO_BRANCH 0
#define BEQ 1
#define BNE 2
#define BLT 3
#define BGT 4
#define BLTU 5
#define BGTU 6
#define NO_ALU 15
#define ADD 0
#define SUB 1
#define SLLA 2
#define SLT 3
#define SLTU 4
#define XOR 5
#define SRL 6
#define SRA 7
#define OR 8
#define AND 9
#define SUBU 10
#define LUI_ALU 11
#define AUIPC_ALU 12
#define CSR_ALU_RW 13
#define CSR_ALU_RS 14
#define CSR_ALU_RC 15
// WRITEBACK
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
// JAL
#define JUMP 1
#define NO_JUMP 0
// STALLS
#define STALL 1
#define NO_STALL 0
#define TAKEN 1
#define NOT_TAKEN 0
#define ZERO_REG 0
// COLORS
#define GREEN "\033[32m"
#define RED "\033[31m"
#define DEFAULT "\033[39m"