minor update

hw/rtl/core/VX_gpr_stage.sv

@@ -8,7 +8,7 @@ module VX_gpr_stage #(
 
     VX_writeback_if.slave   writeback_if,  
     VX_ibuffer_if.gpr       ibuffer_if,
-    VX_gpr_stage_if.slave   gpr_stage_if
+    VX_gpr_stage_if.master  gpr_stage_if
 );
 
     `UNUSED_PARAM (CORE_ID)
@@ -98,7 +98,5 @@ module VX_gpr_stage #(
     `UNUSED_VAR (ibuffer_if.rs3)    
     assign gpr_stage_if.rs3_data = '0;
 `endif
-    
-    assign writeback_if.ready = 1'b1;
 
 endmodule

hw/rtl/core/VX_ibuffer.sv

@@ -89,8 +89,8 @@ module VX_ibuffer #(
         .NUM_INPUTS  (`NUM_WARPS),
         .DATAW       (NW_WIDTH+DATAW),
         .ARBITER     ("R"),
-        .LOCK_ENABLE (1),
-        .BUFFERED    (3)        
+        .LOCK_ENABLE (0),
+        .BUFFERED    (2)        
     ) req_arb (
         .clk       (clk),
         .reset     (reset),

hw/rtl/core/VX_scoreboard.sv

@@ -16,7 +16,7 @@ module VX_scoreboard  #(
     reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
 
     wire reserve_reg = ibuffer_if.valid && ibuffer_if.ready && ibuffer_if.wb;
-    wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
+    wire release_reg = writeback_if.valid && writeback_if.eop;
     
     always @(*) begin
         inuse_regs_n = inuse_regs;
@@ -58,8 +58,6 @@ module VX_scoreboard  #(
     assign used_regs[2] = inuse_regs_n[wid_sel][scoreboard_if.rs2[wid_sel]];
     assign used_regs[3] = inuse_regs_n[wid_sel][scoreboard_if.rs3[wid_sel]];
 
-    `UNUSED_VAR (writeback_if.PC)
-
     always @(posedge clk) begin  
         if (release_reg) begin
             `ASSERT(inuse_regs[writeback_if.wid][writeback_if.rd] != 0,

hw/rtl/core/VX_writeback.sv

@@ -73,7 +73,7 @@ module VX_writeback #(
         }),
         .data_out  ({writeback_if.uuid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop}),
         .valid_out (writeback_if.valid),        
-        .ready_out (writeback_if.ready)
+        .ready_out (1'b1)
     );
 
 `ifdef EXT_F_ENABLE
@@ -84,7 +84,7 @@ module VX_writeback #(
     assign alu_commit_if.ready = wb_alu_ready_in || ~alu_commit_if.wb;
     assign ld_commit_if.ready  = wb_ld_ready_in  || ~ld_commit_if.wb;
 
-    wire writeback_fire = writeback_if.valid && writeback_if.ready;
+    wire writeback_fire = writeback_if.valid;
     
     // simulation helper signal to get RISC-V tests Pass/Fail status
     reg [`NUM_REGS-1:0][`XLEN-1:0] sim_wb_value_r;

hw/rtl/interfaces/VX_gpr_stage_if.sv

@@ -7,15 +7,15 @@ interface VX_gpr_stage_if ();
     wire [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data;
 
     modport master (
-        input rs1_data,
-        input rs2_data,
-        input rs3_data
-    );
-
-    modport slave (
         output rs1_data,
         output rs2_data,
         output rs3_data
     );
 
+    modport slave (
+        input rs1_data,
+        input rs2_data,
+        input rs3_data
+    );
+
 endinterface

hw/rtl/interfaces/VX_ibuffer_if.sv

@@ -62,11 +62,11 @@ interface VX_ibuffer_if ();
     );    
 
     modport scoreboard (
-        input  valid,
-        input  wid,
-        input  wb,
-        input  rd, 
-        output ready
+        input valid,
+        input wid,
+        input wb,
+        input rd, 
+        input ready
     );
     
     modport gpr (

hw/rtl/interfaces/VX_writeback_if.sv

@@ -9,8 +9,7 @@ interface VX_writeback_if ();
     wire [`XLEN-1:0]                PC;
     wire [`NR_BITS-1:0]             rd;
     wire [`NUM_THREADS-1:0][`XLEN-1:0]   data;
-    wire                            eop;    
-    wire                            ready;
+    wire                            eop;
 
     modport master (
         output valid,
@@ -20,8 +19,7 @@ interface VX_writeback_if ();
         output PC,
         output rd,
         output data,
-        output eop,    
-        input  ready
+        output eop
     );
 
     modport slave (
@@ -32,8 +30,7 @@ interface VX_writeback_if ();
         input  PC,
         input  rd,
         input  data,
-        input  eop,
-        output ready
+        input  eop
     );
 
 endinterface