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Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics

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This commit is contained in:
Blaise Tine 2021-03-31 18:36:07 -04:00
commit e6cb148ce1
3 changed files with 89 additions and 60 deletions
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80
hw/rtl/tex_unit/VX_tex_format.v
View file

@ -8,14 +8,17 @@ module VX_tex_format #(
input wire [`TEX_FORMAT_BITS-1:0] format,
output wire [`NUM_COLOR_CHANNEL-1:0] color_enable,
output wire [NUM_TEXELS-1:0][63:0] formatted_texel
output wire [NUM_TEXELS-1:0][63:0] formatted_lerp_texel,
output wire [31:0] formatted_pt_texel
);
`UNUSED_PARAM (CORE_ID)
reg [`NUM_COLOR_CHANNEL-1:0] color_enable_r;
reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
reg [NUM_TEXELS-1:0][63:0] formatted_texel_r;
reg [31:0] formatted_pt_r;
always @(*) begin
// bilerp/trilerp input
for (integer i = 0; i<NUM_TEXELS ;i++ ) begin
case (format)
`TEX_FORMAT_R5G6B5: begin
@ -32,7 +35,31 @@ module VX_tex_format #(
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(texel_data[i][11:8]);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(texel_data[i][15:12]);
if (i == 0)
color_enable_r = 4'b0111;
color_enable_r = 4'b1111;
end
`TEX_FORMAT_L8A8: begin
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(texel_data[i][15:8]);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
if (i == 0)
color_enable_r = 4'b0011;
end
`TEX_FORMAT_A8: begin
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
if (i == 0)
color_enable_r = 4'b0001;
end
`TEX_FORMAT_L8: begin
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
formatted_texel_r[i][23:16] = `TEX_COLOR_BITS'(0);
formatted_texel_r[i][39:32] = `TEX_COLOR_BITS'(0);
formatted_texel_r[i][55:48] = `TEX_COLOR_BITS'(0);
if (i == 0)
color_enable_r = 4'b0001;
end
default: begin // `TEX_FORMAT_R8G8B8A8:
formatted_texel_r[i][07:00] = `TEX_COLOR_BITS'(texel_data[i][7:0]);
@ -44,12 +71,55 @@ module VX_tex_format #(
end
endcase
end
// pt sampling direct output
case (format)
`TEX_FORMAT_R5G6B5: begin
formatted_pt_r[07:00] = {`TEX_COLOR_BITS{1'b1}};
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][4:0]);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][10:5]);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:11]);
end
`TEX_FORMAT_R4G4B4A4: begin
formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][3:0]);
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][7:4]);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][11:8]);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][15:12]);
end
`TEX_FORMAT_L8A8: begin
formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
end
`TEX_FORMAT_A8: begin
formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
end
`TEX_FORMAT_L8: begin
formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(0);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(0);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(0);
end
default: begin // `TEX_FORMAT_R8G8B8A8:
formatted_pt_r[07:00] = `TEX_COLOR_BITS'(texel_data[0][7:0]);
formatted_pt_r[15:08] = `TEX_COLOR_BITS'(texel_data[0][15:8]);
formatted_pt_r[23:16] = `TEX_COLOR_BITS'(texel_data[0][23:16]);
formatted_pt_r[31:24] = `TEX_COLOR_BITS'(texel_data[0][31:24]);
end
endcase
end
assign color_enable = color_enable_r;
assign formatted_pt_texel = formatted_pt_r;
for (genvar i = 0; i < NUM_TEXELS; i++) begin
assign formatted_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
assign formatted_lerp_texel[i] = formatted_texel_r[i] & 64'h00ff00ff00ff00ff;
end
endmodule

12
hw/rtl/tex_unit/VX_tex_sampler.v
View file

@ -34,13 +34,14 @@ module VX_tex_sampler #(
`UNUSED_PARAM (CORE_ID)
wire [`NUM_THREADS-1:0][31:0] req_data;
wire [`NUM_THREADS-1:0][31:0] req_data_bilerp;
wire stall_out;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
wire [31:0] req_data_bilerp;
wire [3:0][63:0] formatted_data;
wire [31:0] formatted_pt_data;
wire [`NUM_COLOR_CHANNEL-1:0] color_enable;
VX_tex_format #(
@ -51,7 +52,8 @@ module VX_tex_sampler #(
.format (req_format),
.color_enable (color_enable),
.formatted_texel(formatted_data)
.formatted_lerp_texel(formatted_data),
.formatted_pt_texel(formatted_pt_data)
);
VX_tex_bilerp #(
@ -63,13 +65,11 @@ module VX_tex_sampler #(
.color_enable (color_enable),
.texels (formatted_data),
.sampled_data (req_data_bilerp[i])
.sampled_data (req_data_bilerp)
);
end
assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? formatted_pt_data : req_data_bilerp;
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign req_data[i] = (req_filter == `TEX_FILTER_BITS'(0)) ? req_texels[i][0] : req_data_bilerp[i];
end
assign stall_out = rsp_valid && ~rsp_ready;

57
hw/unit_tests/tex_unit/tex_sampler/main.cpp
View file

@ -5,48 +5,6 @@
#define MAX_TICKS 20
#define NUM_THREADS
// // outputs
// bool req_ready;
// bool rsp_valid;
// unsigned int rsp_wid;
// unsigned int rsp_tmask;
// unsigned int rsp_PC;
// unsigned int rsp_rd;
// bool rsp_wb;
// unsigned int rsp_data[NUM_THREADS];
// if (input != input_map.end()){
// sim->req_valid = input->req_valid;
// sim->req_wid = input->req_wid;
// sim->req_tmask = input->req_tmask;
// sim->req_PC = input->req_PC;
// sim->req_rd = input->req_rd;
// sim->req_wb = input->req_wb;
// sim->req_filter = input->req_filter;
// sim->req_format = input->req_format;
// // sim->req_u = input->req_u[NUM_THREADS];
// // sim->req_v = input->req_v[NUM_THREADS];
// vl_setw(sim->req_texels, input->req_texels)
// // sim->req_texels = input->req_texels[NUM_THREADS][4];
// sim->rsp_ready = input->rsp_ready;
// } else{
// std::cout << "Warning! No Input on Cycle " << cycle << std::endl;
// }
// if(output != output_map.end()){
// CHECK(sim->req_ready == output->req_ready);
// CHECK(sim->rsp_valid == output->rsp_valid);
// CHECK(sim->rsp_wid == output->rsp_wid);
// CHECK(sim->rsp_tmask == output->rsp_tmask);
// CHECK(sim->rsp_PC == output->rsp_PC);
// CHECK(sim->rsp_rd == output->rsp_rd);
// CHECK(sim->rsp_wb == output->rsp_wb);
// CHECK(vl_cmpw(sim->rsp_data, output->rsp_data));
// }
#define CHECK(x) \
do { \
if (x) \
@ -95,11 +53,11 @@ int main(int argc, char **argv) {
sim->req_PC = 0x0515;
sim->req_wb = 1;
sim->req_filter = 0;
sim->req_format = 3;
vl_setw(sim->req_texels, 0xffff, 0xfffa, 0xfffb, 0xfffc,
0xfffd, 0xafff, 0xbfff, 0xcfff,
0xdfff, 0xabcd, 0xdfdd, 0xeabf,
0xaaaa, 0xbbbb, 0xcccc, 0xdddd);
sim->req_format = 2; //rgba4
vl_setw(sim->req_texels, 0x1234abcd, 0x1234abcd, 0x1234abcd, 0x1234abcd,
0xabcd1234, 0xabcd1234, 0xabcd1234, 0xabcd1234,
0xfaafbaab, 0xfaafbaab, 0xfaafbaab, 0xfaafbaab,
0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef);
sim->rsp_ready = 1;
break;
@ -115,7 +73,7 @@ int main(int argc, char **argv) {
// sim->req_rd = req_rd;
sim->req_wb = 1;
sim->req_filter = 1;
sim->req_format = 3;
sim->req_format = 0;
/*
1u ------- 0u 1v ------- 1v tex0 ------- tex1
| | | | | |
@ -133,7 +91,7 @@ int main(int argc, char **argv) {
0xffffffff, 0x00000000, 0xffffffff, 0x00000000);
// point sampling output check
CHECK(!vl_cmpw(sim->rsp_data, 0xffff, 0xfffd, 0xdfff, 0xaaaa));
CHECK(!vl_cmpw(sim->rsp_data, 0x0a0b0c0d, 0x01020304, 0x0b0a0a0b, 0x0b0e0e0f));
break;
@ -143,6 +101,7 @@ int main(int argc, char **argv) {
sim->rsp_ready = 1;
// bilerp sampling output check
std::cout << "cycle 4: bilerp r8g8b8a8 check" << std::endl;
CHECK(!vl_cmpw(sim->rsp_data, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x3f3f3f3f));