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remove async reset for FPGA synthesis

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codetector 2020-02-19 23:19:05 -05:00
parent 072c89c433
commit e82e29c855
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1 changed files with 3 additions and 3 deletions
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6
rtl/cache/VX_cache_data.v vendored
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@ -79,10 +79,10 @@ module VX_cache_data
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < NUM_IND; ini_ind=ini_ind+1) begin
data[ini_ind] <= 0;
tag[ini_ind] <= 0;
//data[ini_ind] <= 0;
//tag[ini_ind] <= 0;
valid[ini_ind] <= 0;
dirty[ini_ind] <= 0;
//dirty[ini_ind] <= 0;
end
end else begin
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port