mirror of
https://github.com/vortexgpgpu/vortex.git
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fixed FCVT timing critical path
This commit is contained in:
Blaise Tine
parent
a79253329c
commit
e85fa9d842
6 changed files with 139 additions and 131 deletions
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@ -1,14 +1,13 @@
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`include "VX_define.vh"
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`ifndef NOPAE
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import local_mem_cfg_pkg::*;
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`include "afu_json_info.vh"
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`else
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`include "vortex_afu.vh"
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`endif
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/* verilator lint_off IMPORTSTAR */
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import ccip_if_pkg::*;
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import local_mem_cfg_pkg::*;
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/* verilator lint_on IMPORTSTAR */
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`endif
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module vortex_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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@ -3,10 +3,6 @@
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/// Modified port of cast module from fpnew Libray
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/// reference: https://github.com/pulp-platform/fpnew
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`ifndef SYNTHESIS
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`include "float_dpi.vh"
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`endif
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module VX_fp_cvt #(
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parameter TAGW = 1,
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parameter LANES = 1
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@ -73,19 +69,19 @@ module VX_fp_cvt #(
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);
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end
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent;
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wire [LANES-1:0] input_sign;
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent;
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wire [LANES-1:0] input_sign;
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for (genvar i = 0; i < LANES; ++i) begin
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wire [INT_MAN_WIDTH-1:0] int_mantissa;
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wire [INT_MAN_WIDTH-1:0] fmt_mantissa;
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wire fmt_sign = dataa[i][31];
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wire int_sign = dataa[i][31] & is_signed;
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assign int_mantissa = int_sign ? $unsigned(-dataa[i]) : dataa[i];
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assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i];
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assign fmt_mantissa = INT_MAN_WIDTH'({in_a_type[i].is_normal, dataa[i][MAN_BITS-1:0]});
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assign fmt_exponent[i] = $signed({1'b0, dataa[i][MAN_BITS+EXP_BITS-1:MAN_BITS]});
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assign fmt_exponent[i] = {1'b0, dataa[i][MAN_BITS+EXP_BITS-1:MAN_BITS]};
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assign encoded_mant[i] = is_itof ? int_mantissa : fmt_mantissa;
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assign input_sign[i] = is_itof ? int_sign : fmt_sign;
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end
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@ -115,7 +111,7 @@ module VX_fp_cvt #(
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wire [2:0] rnd_mode_s0;
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fp_type_t [LANES-1:0] in_a_type_s0;
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wire [LANES-1:0] input_sign_s0;
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0;
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0;
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0;
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wire [LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0;
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wire [LANES-1:0] mant_is_zero_s0;
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@ -135,38 +131,93 @@ module VX_fp_cvt #(
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// Normalization
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination
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for (genvar i = 0; i < LANES; ++i) begin
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`IGNORE_WARNINGS_BEGIN
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// Input mantissa needs to be normalized
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wire signed [INT_EXP_WIDTH-1:0] fp_input_exp;
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wire signed [INT_EXP_WIDTH-1:0] int_input_exp;
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wire [LZC_RESULT_WIDTH:0] renorm_shamt_sgn;
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// signed form for calculations
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assign renorm_shamt_sgn = $signed({1'b0, renorm_shamt_s0[i]});
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wire [INT_EXP_WIDTH-1:0] fp_input_exp;
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wire [INT_EXP_WIDTH-1:0] int_input_exp;
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// Realign input mantissa, append zeroes if destination is wider
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assign input_mant[i] = encoded_mant_s0[i] << renorm_shamt_s0[i];
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// Unbias exponent and compensate for shift
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assign fp_input_exp = $signed(fmt_exponent_s0[i] +
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(($signed({1'b0, in_a_type_s0[i].is_subnormal}) +
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$signed(FMT_SHIFT_COMPENSATION - EXP_BIAS)) -
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renorm_shamt_sgn));
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assign fp_input_exp = fmt_exponent_s0[i] +
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{1'b0, in_a_type_s0[i].is_subnormal} +
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(FMT_SHIFT_COMPENSATION - EXP_BIAS) -
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{1'b0, renorm_shamt_s0[i]};
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assign int_input_exp = $signed(INT_MAN_WIDTH - 1 - renorm_shamt_sgn);
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assign int_input_exp = (INT_MAN_WIDTH-1) - {1'b0, renorm_shamt_s0[i]};
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assign input_exp[i] = is_itof_s0 ? int_input_exp : fp_input_exp;
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assign input_exp[i] = is_itof_s0 ? int_input_exp : fp_input_exp;
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// Rebias the exponent
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assign destination_exp[i] = input_exp[i] + $signed(EXP_BIAS);
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assign destination_exp[i] = input_exp[i] + EXP_BIAS;
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`IGNORE_WARNINGS_END
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end
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// Perform adjustments to mantissa and exponent
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wire [LANES-1:0][2*INT_MAN_WIDTH:0] preshift_mant_s0;
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wire [LANES-1:0][SHAMT_BITS-1:0] denorm_shamt_s0;
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s0;
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wire [LANES-1:0] of_before_round_s0;
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for (genvar i = 0; i < LANES; ++i) begin
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reg [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift
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reg [SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization
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reg [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments
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reg of_before_round;
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always @(*) begin
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`IGNORE_WARNINGS_BEGIN
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// Default assignment
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final_exp = destination_exp[i]; // take exponent as is, only look at lower bits
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preshift_mant = {input_mant[i], 33'b0}; // Place mantissa to the left of the shifter
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denorm_shamt = 0; // right of mantissa
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of_before_round = 1'b0;
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// Handle INT casts
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if (is_itof_s0) begin
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if ($signed(destination_exp[i]) < $signed(-MAN_BITS)) begin
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// Limit the shift to retain sticky bits
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final_exp = 0; // denormal result
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denorm_shamt = denorm_shamt + (2 + MAN_BITS); // to sticky
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end else if ($signed(destination_exp[i]) < $signed(1)) begin
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// Denormalize underflowing values
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final_exp = 0; // denormal result
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denorm_shamt = denorm_shamt + 1 - destination_exp[i]; // adjust right shifting
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end else if ($signed(destination_exp[i]) >= $signed(2**EXP_BITS-1)) begin
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// Overflow or infinities (for proper rounding)
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final_exp = (2**EXP_BITS-2); // largest normal value
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preshift_mant = ~0; // largest normal value and RS bits set
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of_before_round = 1'b1;
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end
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end else begin
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if ($signed(input_exp[i]) >= $signed((MAX_INT_WIDTH-1) + unsigned_s0)) begin
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// overflow: when converting to unsigned the range is larger by one
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denorm_shamt = SHAMT_BITS'(0); // prevent shifting
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of_before_round = 1'b1;
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end else if ($signed(input_exp[i]) < $signed(-1)) begin
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// underflow
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denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky
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end else begin
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// By default right shift mantissa to be an integer
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denorm_shamt = (MAX_INT_WIDTH-1) - input_exp[i];
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end
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end
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`IGNORE_WARNINGS_END
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end
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assign preshift_mant_s0[i] = preshift_mant;
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assign denorm_shamt_s0[i] = denorm_shamt;
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assign final_exp_s0[i] = final_exp;
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assign of_before_round_s0[i] = of_before_round;
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end
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// Pipeline stage1
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wire valid_in_s1;
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@ -176,121 +227,68 @@ module VX_fp_cvt #(
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wire [2:0] rnd_mode_s1;
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fp_type_t [LANES-1:0] in_a_type_s1;
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wire [LANES-1:0] mant_is_zero_s1;
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wire [LANES-1:0] input_sign_s1;
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1;
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wire signed [LANES-1:0][INT_EXP_WIDTH-1:0] destination_exp_s1;
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wire [LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1;
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wire [LANES-1:0] input_sign_s1;
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wire [LANES-1:0][2*INT_MAN_WIDTH:0] preshift_mant_s1;
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wire [LANES-1:0][SHAMT_BITS-1:0] denorm_shamt_s1;
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wire [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1;
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wire [LANES-1:0] of_before_round_s1;
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VX_pipe_register #(
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.DATAW (1 + TAGW + 1 + `FRM_BITS + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + INT_MAN_WIDTH + 2*INT_EXP_WIDTH)),
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.DATAW (1 + TAGW + 1 + 1 + `FRM_BITS + LANES * ($bits(fp_type_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + SHAMT_BITS + INT_EXP_WIDTH + 1)),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, mant_is_zero_s0, input_sign_s0, input_mant, input_exp, destination_exp}),
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.data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, input_mant_s1, input_exp_s1, destination_exp_s1})
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.data_in ({valid_in_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, in_a_type_s0, mant_is_zero_s0, input_sign_s0, preshift_mant_s0, denorm_shamt_s0, final_exp_s0, of_before_round_s0}),
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.data_out ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, preshift_mant_s1, denorm_shamt_s1, final_exp_s1, of_before_round_s1})
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);
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// Casting
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reg [LANES-1:0][INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments
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reg [LANES-1:0][2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift
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wire [LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant; // mantissa from shifter, with rnd bit
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wire [LANES-1:0][MAN_BITS-1:0] final_mant; // mantissa after adjustments
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wire [LANES-1:0][MAX_INT_WIDTH-1:0] final_int; // integer shifted in position
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reg [LANES-1:0][SHAMT_BITS-1:0] denorm_shamt; // shift amount for denormalization
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wire [LANES-1:0][1:0] fp_round_sticky_bits, int_round_sticky_bits, round_sticky_bits;
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reg [LANES-1:0] of_before_round;
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// Perform adjustments to mantissa and exponent
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wire [LANES-1:0] rounded_sign;
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wire [LANES-1:0][31:0] rounded_abs; // absolute value of result after rounding
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wire [LANES-1:0][1:0] fp_round_sticky_bits, int_round_sticky_bits;
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// Rouding and classification
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for (genvar i = 0; i < LANES; ++i) begin
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always @(*) begin
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`IGNORE_WARNINGS_BEGIN
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// Default assignment
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final_exp[i] = $unsigned(destination_exp_s1[i]); // take exponent as is, only look at lower bits
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preshift_mant[i] = 65'b0; // initialize mantissa container with zeroes
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denorm_shamt[i] = 0; // right of mantissa
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of_before_round[i] = 1'b0;
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// Place mantissa to the left of the shifter
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preshift_mant[i] = {input_mant_s1[i], 33'b0};
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// Handle INT casts
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if (is_itof_s1) begin
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// Overflow or infinities (for proper rounding)
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if ($signed(destination_exp_s1[i]) >= $signed(2**EXP_BITS-1)) begin
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final_exp[i] = (2**EXP_BITS-2); // largest normal value
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preshift_mant[i] = ~0; // largest normal value and RS bits set
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of_before_round[i] = 1'b1;
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// Denormalize underflowing values
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end else if (($signed(destination_exp_s1[i]) < $signed(1))
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&& ($signed(destination_exp_s1[i]) >= -$signed(MAN_BITS))) begin
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final_exp[i] = 0; // denormal result
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denorm_shamt[i] = $unsigned(denorm_shamt[i] + 1 - destination_exp_s1[i]); // adjust right shifting
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// Limit the shift to retain sticky bits
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end else if ($signed(destination_exp_s1[i]) < -$signed(MAN_BITS)) begin
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final_exp[i] = 0; // denormal result
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denorm_shamt[i] = $unsigned(denorm_shamt[i] + (2 + MAN_BITS)); // to sticky
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end
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end else begin
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// By default right shift mantissa to be an integer
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denorm_shamt[i] = (MAX_INT_WIDTH-1) - input_exp_s1[i];
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// overflow: when converting to unsigned the range is larger by one
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if ($signed(input_exp_s1[i]) >= $signed(MAX_INT_WIDTH -1 + unsigned_s1)) begin
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denorm_shamt[i] = SHAMT_BITS'(0); // prevent shifting
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of_before_round[i] = 1'b1;
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// underflow
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end else if ($signed(input_exp_s1[i]) < $signed(-1)) begin
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denorm_shamt[i] = MAX_INT_WIDTH + 1; // all bits go to the sticky
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end
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end
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`IGNORE_WARNINGS_END
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end
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wire [2*INT_MAN_WIDTH:0] destination_mant;
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wire [MAN_BITS-1:0] final_mant; // mantissa after adjustments
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wire [MAX_INT_WIDTH-1:0] final_int; // integer shifted in position
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wire [1:0] round_sticky_bits;
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wire [31:0] fmt_pre_round_abs;
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wire [31:0] pre_round_abs;
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// Mantissa adjustment shift
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assign destination_mant[i] = preshift_mant[i] >> denorm_shamt[i];
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assign destination_mant = preshift_mant_s1[i] >> denorm_shamt_s1[i];
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// Extract final mantissa and round bit, discard the normal bit (for FP)
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assign {final_mant[i], fp_round_sticky_bits[i][1]} = destination_mant[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1];
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assign {final_int[i], int_round_sticky_bits[i][1]} = destination_mant[i][2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1];
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assign {final_mant, fp_round_sticky_bits[i][1]} = destination_mant[2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1];
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assign {final_int, int_round_sticky_bits[i][1]} = destination_mant[2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1];
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// Collapse sticky bits
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assign fp_round_sticky_bits[i][0] = (| destination_mant[i][NUM_FP_STICKY-1:0]);
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assign int_round_sticky_bits[i][0] = (| destination_mant[i][NUM_INT_STICKY-1:0]);
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assign fp_round_sticky_bits[i][0] = (| destination_mant[NUM_FP_STICKY-1:0]);
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assign int_round_sticky_bits[i][0] = (| destination_mant[NUM_INT_STICKY-1:0]);
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// select RS bits for destination operation
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assign round_sticky_bits[i] = is_itof_s1 ? fp_round_sticky_bits[i] : int_round_sticky_bits[i];
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end
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assign round_sticky_bits = is_itof_s1 ? fp_round_sticky_bits[i] : int_round_sticky_bits[i];
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// Rouding and classification
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wire [LANES-1:0] rounded_sign;
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wire [LANES-1:0][31:0] rounded_abs; // absolute value of result after rounding
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for (genvar i = 0; i < LANES; ++i) begin
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// Pack exponent and mantissa into proper rounding form
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wire [31:0] fmt_pre_round_abs = {1'b0, final_exp[i][EXP_BITS-1:0], final_mant[i][MAN_BITS-1:0]};
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// Sign-extend integer result
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wire [31:0] ifmt_pre_round_abs = final_int[i];
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assign fmt_pre_round_abs = {1'b0, final_exp_s1[i][EXP_BITS-1:0], final_mant[MAN_BITS-1:0]};
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// Select output with destination format and operation
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wire [31:0] pre_round_abs = is_itof_s1 ? fmt_pre_round_abs : ifmt_pre_round_abs;
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assign pre_round_abs = is_itof_s1 ? fmt_pre_round_abs : final_int;
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// Perform the rounding
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VX_fp_rounding #(
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.DAT_WIDTH (32)
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) fp_rounding (
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.abs_value_i (pre_round_abs),
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.sign_i (input_sign_s1[i]),
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.round_sticky_bits_i (round_sticky_bits[i]),
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.rnd_mode_i (rnd_mode_s1),
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.effective_subtraction_i (1'b0),
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.abs_rounded_o (rounded_abs[i]),
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.sign_o (rounded_sign[i]),
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.abs_value_i (pre_round_abs),
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.sign_i (input_sign_s1[i]),
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.round_sticky_bits_i(round_sticky_bits),
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.rnd_mode_i (rnd_mode_s1),
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.effective_subtraction_i(1'b0),
|
||||
.abs_rounded_o (rounded_abs[i]),
|
||||
.sign_o (rounded_sign[i]),
|
||||
`UNUSED_PIN (exact_zero_o)
|
||||
);
|
||||
end
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|
|
@ -306,23 +304,22 @@ module VX_fp_cvt #(
|
|||
wire [LANES-1:0] input_sign_s2;
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wire [LANES-1:0] rounded_sign_s2;
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wire [LANES-1:0][31:0] rounded_abs_s2;
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wire [LANES-1:0] of_before_round_s2;
|
||||
|
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VX_pipe_register #(
|
||||
.DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + 32 + 1)),
|
||||
.DATAW (1 + TAGW + 1 + 1 + LANES * ($bits(fp_type_t) + 1 + 1 + 32 + 1 + 1)),
|
||||
.RESETW (1)
|
||||
) pipe_reg2 (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.enable (~stall),
|
||||
.data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, rounded_abs, rounded_sign}),
|
||||
.data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, in_a_type_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2})
|
||||
.data_in ({valid_in_s1, tag_in_s1, is_itof_s1, unsigned_s1, in_a_type_s1, mant_is_zero_s1, input_sign_s1, rounded_abs, rounded_sign, of_before_round_s1}),
|
||||
.data_out ({valid_in_s2, tag_in_s2, is_itof_s2, unsigned_s2, in_a_type_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2, of_before_round_s2})
|
||||
);
|
||||
|
||||
wire [LANES-1:0] of_after_round;
|
||||
wire [LANES-1:0] uf_after_round;
|
||||
|
||||
wire [LANES-1:0][31:0] fmt_result;
|
||||
|
||||
wire [LANES-1:0][31:0] rounded_int_res; // after possible inversion
|
||||
wire [LANES-1:0] rounded_int_res_zero; // after rounding
|
||||
|
||||
|
|
@ -335,7 +332,7 @@ module VX_fp_cvt #(
|
|||
assign of_after_round[i] = (rounded_abs_s2[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == ~0); // inf exp.
|
||||
|
||||
// Negative integer result needs to be brought into two's complement
|
||||
assign rounded_int_res[i] = rounded_sign_s2[i] ? $unsigned(-rounded_abs_s2[i]) : rounded_abs_s2[i];
|
||||
assign rounded_int_res[i] = rounded_sign_s2[i] ? (-rounded_abs_s2[i]) : rounded_abs_s2[i];
|
||||
assign rounded_int_res_zero[i] = (rounded_int_res[i] == 0);
|
||||
end
|
||||
|
||||
|
|
@ -373,7 +370,7 @@ module VX_fp_cvt #(
|
|||
int_special_result[i][30:0] = 0; // alone yields 2**(31)-1
|
||||
int_special_result[i][31] = ~unsigned_s2; // for unsigned casts yields 2**31
|
||||
end else begin
|
||||
int_special_result[i][30:0] = 2**(31) -1; // alone yields 2**(31)-1
|
||||
int_special_result[i][30:0] = 2**(31) - 1; // alone yields 2**(31)-1
|
||||
int_special_result[i][31] = unsigned_s2; // for unsigned casts yields 2**31
|
||||
end
|
||||
end
|
||||
|
|
@ -381,7 +378,7 @@ module VX_fp_cvt #(
|
|||
// Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned)
|
||||
assign int_result_is_special[i] = in_a_type_s2[i].is_nan
|
||||
| in_a_type_s2[i].is_inf
|
||||
| of_before_round[i]
|
||||
| of_before_round_s2[i]
|
||||
| (input_sign_s2[i] & unsigned_s2 & ~rounded_int_res_zero[i]);
|
||||
|
||||
// All integer special cases are invalid
|
||||
|
|
@ -399,11 +396,11 @@ module VX_fp_cvt #(
|
|||
wire [31:0] fp_result, int_result;
|
||||
|
||||
wire inexact = is_itof_s2 ? (| fp_round_sticky_bits[i]) // overflow is invalid in i2f;
|
||||
: (| fp_round_sticky_bits[i]) | (~in_a_type_s2[i].is_inf & (of_before_round[i] | of_after_round[i]));
|
||||
: (| fp_round_sticky_bits[i]) | (~in_a_type_s2[i].is_inf & (of_before_round_s2[i] | of_after_round[i]));
|
||||
|
||||
assign fp_regular_status.NV = is_itof_s2 & (of_before_round[i] | of_after_round[i]); // overflow is invalid for I2F casts
|
||||
assign fp_regular_status.NV = is_itof_s2 & (of_before_round_s2[i] | of_after_round[i]); // overflow is invalid for I2F casts
|
||||
assign fp_regular_status.DZ = 1'b0; // no divisions
|
||||
assign fp_regular_status.OF = ~is_itof_s2 & (~in_a_type_s2[i].is_inf & (of_before_round[i] | of_after_round[i])); // inf casts no OF
|
||||
assign fp_regular_status.OF = ~is_itof_s2 & (~in_a_type_s2[i].is_inf & (of_before_round_s2[i] | of_after_round[i])); // inf casts no OF
|
||||
assign fp_regular_status.UF = uf_after_round[i] & inexact;
|
||||
assign fp_regular_status.NX = inexact;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
`include "float_dpi.vh"
|
||||
`endif
|
||||
|
||||
module VX_fp_div #(
|
||||
parameter TAGW = 1,
|
||||
parameter LANES = 1
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
`include "float_dpi.vh"
|
||||
`endif
|
||||
|
||||
module VX_fp_fma #(
|
||||
parameter TAGW = 1,
|
||||
parameter LANES = 1
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
`include "VX_define.vh"
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
`include "float_dpi.vh"
|
||||
`endif
|
||||
|
||||
module VX_fp_sqrt #(
|
||||
parameter TAGW = 1,
|
||||
parameter LANES = 1
|
||||
|
|
@ -44,7 +48,7 @@ module VX_fp_sqrt #(
|
|||
fflags_t f;
|
||||
|
||||
always @(*) begin
|
||||
dpi_fsqrt (dataa[i], frm, r, f);
|
||||
dpi_fsqrt (dataa[i], frm, r, f);
|
||||
end
|
||||
`UNUSED_VAR (f)
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ module VX_fp_type (
|
|||
);
|
||||
wire is_normal = (exp_i != 8'd0) && (exp_i != 8'hff);
|
||||
wire is_zero = (exp_i == 8'd0) && (man_i == 23'd0);
|
||||
wire is_subnormal = (exp_i == 8'd0) && !is_zero;
|
||||
wire is_subnormal = (exp_i == 8'd0) && (man_i != 23'd0);
|
||||
wire is_inf = (exp_i == 8'hff) && (man_i == 23'd0);
|
||||
wire is_nan = (exp_i == 8'hff) && (man_i != 23'd0);
|
||||
wire is_signaling = is_nan && (man_i[22] == 1'b0);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue