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renamed gbar_bus_if

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This commit is contained in:
Blaise Tine 2023-06-22 06:41:11 -04:00
parent b0bc75f956
commit e8e3ce6a4d
8 changed files with 63 additions and 63 deletions
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16
hw/rtl/VX_cluster.sv
View file

@ -77,8 +77,8 @@ module VX_cluster #(
`SCOPE_IO_SWITCH (scope_raster_units + `NUM_SOCKETS);
`endif
VX_gbar_if per_socket_gbar_if[`NUM_SOCKETS]();
VX_gbar_if gbar_if();
VX_gbar_bus_if per_socket_gbar_bus_if[`NUM_SOCKETS]();
VX_gbar_bus_if gbar_bus_if();
`RESET_RELAY (gbar_reset, reset);
@ -87,16 +87,16 @@ module VX_cluster #(
) gbar_arb (
.clk (clk),
.reset (gbar_reset),
.req_in_if (per_socket_gbar_if),
.req_out_if (gbar_if)
.bus_in_if (per_socket_gbar_bus_if),
.bus_out_if (gbar_bus_if)
);
VX_gbar_unit #(
.INSTANCE_ID ($sformatf("gbar%0d", CLUSTER_ID))
) gbar_unit (
.clk (clk),
.reset (gbar_reset),
.gbar_if (gbar_if)
.clk (clk),
.reset (gbar_reset),
.gbar_bus_if (gbar_bus_if)
);
`ifdef EXT_RASTER_ENABLE
@ -541,7 +541,7 @@ module VX_cluster #(
.rop_req_if (per_socket_rop_req_if[i]),
`endif
.gbar_if (per_socket_gbar_if[i]),
.gbar_bus_if (per_socket_gbar_bus_if[i]),
.sim_ebreak (per_socket_sim_ebreak[i]),
.sim_wb_value (per_socket_sim_wb_value[i]),

28
hw/rtl/VX_gbar_arb.sv
View file

@ -5,11 +5,11 @@ module VX_gbar_arb #(
parameter BUFFERED_REQ = 0,
parameter `STRING ARBITER = "R"
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
VX_gbar_if.slave req_in_if[NUM_REQS],
VX_gbar_if.master req_out_if
VX_gbar_bus_if.slave bus_in_if[NUM_REQS],
VX_gbar_bus_if.master bus_out_if
);
localparam REQ_DATAW = `NB_BITS + `UP(`NC_BITS) + `UP(`NC_BITS);
@ -21,9 +21,9 @@ module VX_gbar_arb #(
wire [NUM_REQS-1:0] req_ready_in;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign req_valid_in[i] = req_in_if[i].req_valid;
assign req_data_in[i] = {req_in_if[i].req_id, req_in_if[i].req_size_m1, req_in_if[i].req_core_id};
assign req_in_if[i].req_ready = req_ready_in[i];
assign req_valid_in[i] = bus_in_if[i].req_valid;
assign req_data_in[i] = {bus_in_if[i].req_id, bus_in_if[i].req_size_m1, bus_in_if[i].req_core_id};
assign bus_in_if[i].req_ready = req_ready_in[i];
end
VX_stream_arb #(
@ -39,9 +39,9 @@ module VX_gbar_arb #(
.valid_in (req_valid_in),
.ready_in (req_ready_in),
.data_in (req_data_in),
.data_out ({req_out_if.req_id, req_out_if.req_size_m1, req_out_if.req_core_id}),
.valid_out (req_out_if.req_valid),
.ready_out (req_out_if.req_ready)
.data_out ({bus_out_if.req_id, bus_out_if.req_size_m1, bus_out_if.req_core_id}),
.valid_out (bus_out_if.req_valid),
.ready_out (bus_out_if.req_ready)
);
// broadcast response
@ -53,14 +53,14 @@ module VX_gbar_arb #(
if (reset) begin
rsp_valid <= 0;
end else begin
rsp_valid <= req_out_if.rsp_valid;
rsp_valid <= bus_out_if.rsp_valid;
end
rsp_id <= req_out_if.rsp_id;
rsp_id <= bus_out_if.rsp_id;
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign req_in_if[i].rsp_valid = rsp_valid;
assign req_in_if[i].rsp_id = rsp_id;
assign bus_in_if[i].rsp_valid = rsp_valid;
assign bus_in_if[i].rsp_id = rsp_id;
end
endmodule

28
hw/rtl/VX_gbar_unit.sv
View file

@ -6,14 +6,14 @@ module VX_gbar_unit #(
input wire clk,
input wire reset,
VX_gbar_if.slave gbar_if
VX_gbar_bus_if.slave gbar_bus_if
);
`UNUSED_SPARAM (INSTANCE_ID)
localparam NC_WIDTH = `UP(`NC_BITS);
reg [`NB_BITS-1:0][`NUM_CORES-1:0] barrier_masks;
wire [`CLOG2(`NUM_CORES+1)-1:0] active_barrier_count;
wire [`NUM_CORES-1:0] curr_barrier_mask = barrier_masks[gbar_if.req_id];
wire [`NUM_CORES-1:0] curr_barrier_mask = barrier_masks[gbar_bus_if.req_id];
`POP_COUNT(active_barrier_count, curr_barrier_mask);
`UNUSED_VAR (active_barrier_count)
@ -29,30 +29,30 @@ module VX_gbar_unit #(
if (rsp_valid) begin
rsp_valid <= 0;
end
if (gbar_if.req_valid) begin
if (active_barrier_count[NC_WIDTH-1:0] == gbar_if.req_size_m1) begin
barrier_masks[gbar_if.req_id] <= '0;
if (gbar_bus_if.req_valid) begin
if (active_barrier_count[NC_WIDTH-1:0] == gbar_bus_if.req_size_m1) begin
barrier_masks[gbar_bus_if.req_id] <= '0;
rsp_valid <= 1;
rsp_bar_id <= gbar_if.req_id;
rsp_bar_id <= gbar_bus_if.req_id;
end else begin
barrier_masks[gbar_if.req_id][gbar_if.req_core_id] <= 1;
barrier_masks[gbar_bus_if.req_id][gbar_bus_if.req_core_id] <= 1;
end
end
end
end
assign gbar_if.rsp_valid = rsp_valid;
assign gbar_if.rsp_id = rsp_bar_id;
assign gbar_if.req_ready = 1; // global barrier unit is always ready (no dependencies)
assign gbar_bus_if.rsp_valid = rsp_valid;
assign gbar_bus_if.rsp_id = rsp_bar_id;
assign gbar_bus_if.req_ready = 1; // global barrier unit is always ready (no dependencies)
`ifdef DBG_TRACE_GBAR
always @(posedge clk) begin
if (gbar_if.req_valid && gbar_if.req_ready) begin
if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin
`TRACE(1, ("%d: %s-acquire: bar_id=%0d, size=%0d, core_id=%0d\n",
$time, INSTANCE_ID, gbar_if.req_id, gbar_if.req_size_m1, gbar_if.req_core_id));
$time, INSTANCE_ID, gbar_bus_if.req_id, gbar_bus_if.req_size_m1, gbar_bus_if.req_core_id));
end
if (gbar_if.rsp_valid) begin
`TRACE(1, ("%d: %s-release: bar_id=%0d\n", $time, INSTANCE_ID, gbar_if.rsp_id));
if (gbar_bus_if.rsp_valid) begin
`TRACE(1, ("%d: %s-release: bar_id=%0d\n", $time, INSTANCE_ID, gbar_bus_if.rsp_id));
end
end
`endif

10
hw/rtl/VX_socket.sv
View file

@ -56,7 +56,7 @@ module VX_socket #(
VX_rop_req_if.master rop_req_if,
`endif
VX_gbar_if.master gbar_if,
VX_gbar_bus_if.master gbar_bus_if,
// simulation helper signals
@ -67,7 +67,7 @@ module VX_socket #(
output wire busy
);
VX_gbar_if per_core_gbar_if[`SOCKET_SIZE]();
VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE]();
`RESET_RELAY (gbar_arb_reset, reset);
@ -76,8 +76,8 @@ module VX_socket #(
) gbar_arb (
.clk (clk),
.reset (gbar_arb_reset),
.req_in_if (per_core_gbar_if),
.req_out_if (gbar_if)
.bus_in_if (per_core_gbar_bus_if),
.bus_out_if (gbar_bus_if)
);
`ifdef EXT_RASTER_ENABLE
@ -390,7 +390,7 @@ module VX_socket #(
.rop_req_if (per_core_rop_req_if[i]),
`endif
.gbar_if (per_core_gbar_if[i]),
.gbar_bus_if (per_core_gbar_bus_if[i]),
.sim_ebreak (per_core_sim_ebreak[i]),
.sim_wb_value (per_core_sim_wb_value[i]),

22
hw/rtl/core/VX_core.sv
View file

@ -75,7 +75,7 @@ module VX_core #(
VX_rop_req_if.master rop_req_if,
`endif
VX_gbar_if.master gbar_if,
VX_gbar_bus_if.master gbar_bus_if,
// simulation helper signals
output wire sim_ebreak,
@ -144,7 +144,7 @@ module VX_core #(
.wrelease_if (wrelease_if),
.join_if (join_if),
.warp_ctl_if (warp_ctl_if),
.gbar_if (gbar_if),
.gbar_bus_if (gbar_bus_if),
.branch_ctl_if (branch_ctl_if),
.ifetch_rsp_if (ifetch_rsp_if),
.fetch_to_csr_if(fetch_to_csr_if),
@ -463,15 +463,15 @@ module VX_core_top #(
output wire busy
);
VX_gbar_if gbar_if();
VX_gbar_bus_if gbar_bus_if();
assign gbar_req_valid = gbar_if.req_valid;
assign gbar_req_id = gbar_if.req_id;
assign gbar_req_size_m1 = gbar_if.req_size_m1;
assign gbar_req_core_id = gbar_if.req_core_id;
assign gbar_if.req_ready = gbar_req_ready;
assign gbar_if.rsp_valid = gbar_rsp_valid;
assign gbar_if.rsp_id = gbar_rsp_id;
assign gbar_req_valid = gbar_bus_if.req_valid;
assign gbar_req_id = gbar_bus_if.req_id;
assign gbar_req_size_m1 = gbar_bus_if.req_size_m1;
assign gbar_req_core_id = gbar_bus_if.req_core_id;
assign gbar_bus_if.req_ready = gbar_req_ready;
assign gbar_bus_if.rsp_valid = gbar_rsp_valid;
assign gbar_bus_if.rsp_id = gbar_rsp_id;
VX_dcr_write_if dcr_write_if();
@ -649,7 +649,7 @@ module VX_core_top #(
`ifdef EXT_ROP_ENABLE
.rop_req_if (rop_req_if),
`endif
.gbar_if (gbar_if),
.gbar_bus_if (gbar_bus_if),
.sim_ebreak (sim_ebreak),
.sim_wb_value (sim_wb_value),

4
hw/rtl/core/VX_fetch.sv
View file

@ -27,7 +27,7 @@ module VX_fetch #(
// outputs
VX_ifetch_rsp_if.master ifetch_rsp_if,
VX_gbar_if.master gbar_if,
VX_gbar_bus_if.master gbar_bus_if,
// csr interface
VX_fetch_to_csr_if.master fetch_to_csr_if,
@ -55,7 +55,7 @@ module VX_fetch #(
.branch_ctl_if (branch_ctl_if),
.ifetch_req_if (ifetch_req_if),
.gbar_if (gbar_if),
.gbar_bus_if (gbar_bus_if),
.fetch_to_csr_if(fetch_to_csr_if),

16
hw/rtl/core/VX_warp_sched.sv
View file

@ -19,7 +19,7 @@ module VX_warp_sched #(
VX_branch_ctl_if.slave branch_ctl_if,
VX_ifetch_req_if.master ifetch_req_if,
VX_gbar_if.master gbar_if,
VX_gbar_bus_if.master gbar_bus_if,
VX_fetch_to_csr_if.master fetch_to_csr_if,
@ -133,8 +133,8 @@ module VX_warp_sched #(
barrier_masks[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1;
end
end
if (gbar_if.rsp_valid && (gbar_req_id == gbar_if.rsp_id)) begin
barrier_masks[gbar_if.rsp_id] <= '0;
if (gbar_bus_if.rsp_valid && (gbar_req_id == gbar_bus_if.rsp_id)) begin
barrier_masks[gbar_bus_if.rsp_id] <= '0;
end
// TMC handling
@ -187,7 +187,7 @@ module VX_warp_sched #(
active_warps <= active_warps_n;
end
if (gbar_if.req_valid && gbar_if.req_ready) begin
if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin
gbar_req_valid <= 0;
end
end
@ -212,10 +212,10 @@ module VX_warp_sched #(
end
end
assign gbar_if.req_valid = gbar_req_valid;
assign gbar_if.req_id = gbar_req_id;
assign gbar_if.req_size_m1 = gbar_req_size_m1;
assign gbar_if.req_core_id = NC_WIDTH'(CORE_ID % `NUM_CORES);
assign gbar_bus_if.req_valid = gbar_req_valid;
assign gbar_bus_if.req_id = gbar_req_id;
assign gbar_bus_if.req_size_m1 = gbar_req_size_m1;
assign gbar_bus_if.req_core_id = NC_WIDTH'(CORE_ID % `NUM_CORES);
// split/join stack management

2
hw/rtl/interfaces/VX_gbar_if.sv → hw/rtl/interfaces/VX_gbar_bus_if.sv
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
interface VX_gbar_if ();
interface VX_gbar_bus_if ();
wire req_valid;
wire [`NB_BITS-1:0] req_id;