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fixed BRAM multi-dimensional array bug on Xilinx Vivado

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This commit is contained in:
Blaise Tine 2024-09-27 09:13:24 -07:00
parent 5db1937a5e
commit e9f19a0bf9
1 changed files with 5 additions and 3 deletions
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8
hw/rtl/libs/VX_mem_scheduler.sv
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@ -460,14 +460,15 @@ module VX_mem_scheduler #(
end else begin : g_rsp_full
reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store [CORE_QUEUE_SIZE-1:0];
reg [CORE_BATCHES-1:00][CORE_CHANNELS-1:0][WORD_WIDTH-1:0] rsp_store_n;
reg [CORE_BATCHES*CORE_CHANNELS*WORD_WIDTH-1:0] rsp_store_n; // use flattened array for BRAM synthesis compatibility
reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0];
always @(*) begin
rsp_store_n = rsp_store[ibuf_raddr];
for (integer i = 0; i < CORE_CHANNELS; ++i) begin
if ((CORE_CHANNELS == 1) || mem_rsp_mask_s[i]) begin
rsp_store_n[rsp_batch_idx][i] = mem_rsp_data_s[i];
integer k = (rsp_batch_idx * CORE_CHANNELS * WORD_WIDTH) + (i * WORD_WIDTH);
rsp_store_n[k +: WORD_WIDTH] = mem_rsp_data_s[i];
end
end
end
@ -488,7 +489,8 @@ module VX_mem_scheduler #(
for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data
localparam i = r / CORE_CHANNELS;
localparam j = r % CORE_CHANNELS;
assign crsp_data[r] = rsp_store_n[i][j];
localparam k = (i * CORE_CHANNELS * WORD_WIDTH) + (j * WORD_WIDTH);
assign crsp_data[r] = rsp_store_n[k +: WORD_WIDTH];
end
assign mem_rsp_ready_s = crsp_ready || ~rsp_complete;