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customizing the memory address bus width

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This commit is contained in:
Blaise Tine 2023-06-25 12:46:29 -04:00
parent e714c86e65
commit ea59247048
11 changed files with 30 additions and 22 deletions
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8
hw/rtl/VX_config.vh
View file

@ -94,6 +94,14 @@
`define MEM_BLOCK_SIZE 64
`endif
`ifndef MEM_ADDR_WIDTH
`ifdef XLEN_64
`define MEM_ADDR_WIDTH 48
`else
`define MEM_ADDR_WIDTH 32
`endif
`endif
`ifndef L1_LINE_SIZE
`ifdef L1_DISABLE
`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE)

4
hw/rtl/VX_define.vh
View file

@ -302,14 +302,14 @@
`endif
`define VX_MEM_BYTEEN_WIDTH `L3_LINE_SIZE
`define VX_MEM_ADDR_WIDTH (`XLEN - `CLOG2(`L3_LINE_SIZE))
`define VX_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE))
`define VX_MEM_DATA_WIDTH (`L3_LINE_SIZE * 8)
`define VX_MEM_TAG_WIDTH L3_MEM_TAG_WIDTH
`define VX_DCR_ADDR_WIDTH `VX_DCR_ADDR_BITS
`define VX_DCR_DATA_WIDTH 32
`define TO_FULL_ADDR(x) {x, (`XLEN-$bits(x))'(0)}
`define TO_FULL_ADDR(x) {x, (`MEM_ADDR_WIDTH-$bits(x))'(0)}
///////////////////////////////////////////////////////////////////////////////

2
hw/rtl/cache/VX_cache_arb.sv vendored
View file

@ -18,7 +18,7 @@ module VX_cache_arb #(
VX_cache_bus_if.master bus_out_if [NUM_OUTPUTS]
);
localparam ADDR_WIDTH = (`XLEN-`CLOG2(DATA_SIZE));
localparam ADDR_WIDTH = (`MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE));
localparam DATA_WIDTH = (8 * DATA_SIZE);
localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS);
localparam NUM_REQS = 1 << LOG_NUM_REQS;

2
hw/rtl/cache/VX_cache_bus_if.sv vendored
View file

@ -4,7 +4,7 @@ interface VX_cache_bus_if #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_WIDTH = 1,
parameter ADDR_WIDTH = `XLEN - `CLOG2(WORD_SIZE),
parameter ADDR_WIDTH = `MEM_ADDR_WIDTH - `CLOG2(WORD_SIZE),
parameter DATA_WIDTH = WORD_SIZE * 8
) ();

4
hw/rtl/cache/VX_cache_define.vh vendored
View file

@ -16,8 +16,8 @@
`define CS_LINES_PER_BANK (`CS_BANK_SIZE / (LINE_SIZE * NUM_WAYS))
`define CS_WORDS_PER_LINE (LINE_SIZE / WORD_SIZE)
`define CS_WORD_ADDR_WIDTH (`XLEN-`CLOG2(WORD_SIZE))
`define CS_MEM_ADDR_WIDTH (`XLEN-`CLOG2(LINE_SIZE))
`define CS_WORD_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(WORD_SIZE))
`define CS_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(LINE_SIZE))
`define CS_LINE_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS))
// Word select

2
hw/rtl/core/VX_fetch.sv
View file

@ -83,7 +83,7 @@ module VX_fetch #(
// Icache Request
assign icache_req_valid = schedule_if.valid && ~pending_ibuf_full[schedule_if.wid];
assign icache_req_addr = schedule_if.PC[`XLEN-1:2];
assign icache_req_addr = schedule_if.PC[`MEM_ADDR_WIDTH-1:2];
assign icache_req_tag = {schedule_if.uuid, req_tag};
assign schedule_if.ready = icache_req_ready && ~pending_ibuf_full[schedule_if.wid];

10
hw/rtl/core/VX_gpu_types.vh
View file

@ -42,7 +42,7 @@ typedef struct packed {
// Word size in bytes
localparam ICACHE_WORD_SIZE = 4;
localparam ICACHE_ADDR_WIDTH = (`XLEN - `CLOG2(ICACHE_WORD_SIZE));
localparam ICACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(ICACHE_WORD_SIZE));
// Block size in bytes
localparam ICACHE_LINE_SIZE = `L1_LINE_SIZE;
@ -71,7 +71,7 @@ localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(ICACHE_NUM_REQ
// Word size in bytes
localparam DCACHE_WORD_SIZE = (`XLEN / 8);
localparam DCACHE_ADDR_WIDTH = (`XLEN - `CLOG2(DCACHE_WORD_SIZE));
localparam DCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(DCACHE_WORD_SIZE));
// Block size in bytes
localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE;
@ -109,7 +109,7 @@ localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_BYPASS_TAG_WIDTH(DCACHE_NUM_
// Word size in bytes
localparam TCACHE_WORD_SIZE = 4;
localparam TCACHE_ADDR_WIDTH = (`XLEN - `CLOG2(TCACHE_WORD_SIZE));
localparam TCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(TCACHE_WORD_SIZE));
// Block size in bytes
localparam TCACHE_LINE_SIZE = `L1_LINE_SIZE;
@ -143,7 +143,7 @@ localparam TCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(TCACHE_NUM_REQ
// Word size in bytes
localparam RCACHE_WORD_SIZE = 4;
localparam RCACHE_ADDR_WIDTH = (`XLEN - `CLOG2(RCACHE_WORD_SIZE));
localparam RCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(RCACHE_WORD_SIZE));
// Block size in bytes
localparam RCACHE_LINE_SIZE = `L1_LINE_SIZE;
@ -177,7 +177,7 @@ localparam RCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_TAG_WIDTH(RCACHE_NUM_REQ
// Word size in bytes
localparam OCACHE_WORD_SIZE = 4;
localparam OCACHE_ADDR_WIDTH = (`XLEN - `CLOG2(OCACHE_WORD_SIZE));
localparam OCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(OCACHE_WORD_SIZE));
// Block size in bytes
localparam OCACHE_LINE_SIZE = `L1_LINE_SIZE;

4
hw/rtl/core/VX_lsu_unit.sv
View file

@ -112,7 +112,7 @@ module VX_lsu_unit #(
wire mem_req_valid;
wire [`NUM_THREADS-1:0] mem_req_mask;
wire mem_req_rw;
wire [`NUM_THREADS-1:0][`XLEN-REQ_ASHIFT-1:0] mem_req_addr;
wire [`NUM_THREADS-1:0][`MEM_ADDR_WIDTH-REQ_ASHIFT-1:0] mem_req_addr;
reg [`NUM_THREADS-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen;
reg [`NUM_THREADS-1:0][`XLEN-1:0] mem_req_data;
wire [TAG_WIDTH-1:0] mem_req_tag;
@ -140,7 +140,7 @@ module VX_lsu_unit #(
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0];
assign mem_req_addr[i] = full_addr[i][`XLEN-1:REQ_ASHIFT];
assign mem_req_addr[i] = full_addr[i][`MEM_ADDR_WIDTH-1:REQ_ASHIFT];
end
// data formatting

6
hw/rtl/mem/VX_mem_arb.sv
View file

@ -3,13 +3,13 @@
module VX_mem_arb #(
parameter NUM_REQS = 1,
parameter DATA_WIDTH = 1,
parameter DATA_SIZE = (DATA_WIDTH / 8),
parameter ADDR_WIDTH = (`XLEN - `CLOG2(DATA_SIZE)),
parameter ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE)),
parameter TAG_WIDTH = 1,
parameter TAG_SEL_IDX = 0,
parameter BUFFERED_REQ = 0,
parameter BUFFERED_RSP = 0,
parameter `STRING ARBITER = "R"
parameter `STRING ARBITER = "R",
parameter DATA_SIZE = (DATA_WIDTH / 8)
) (
input wire clk,
input wire reset,

8
hw/rtl/mem/VX_mem_bus_if.sv
View file

@ -1,10 +1,10 @@
`include "VX_define.vh"
interface VX_mem_bus_if #(
parameter DATA_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8,
parameter ADDR_WIDTH = `XLEN - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1
parameter DATA_WIDTH = 1,
parameter ADDR_WIDTH = `MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE),
parameter TAG_WIDTH = 1,
parameter DATA_SIZE = DATA_WIDTH / 8
) ();
wire req_valid;

2
hw/rtl/mem/VX_smem_switch.sv
View file

@ -16,7 +16,7 @@ module VX_smem_switch #(
VX_cache_bus_if.slave bus_in_if,
VX_cache_bus_if.master bus_out_if [NUM_REQS]
);
localparam ADDR_WIDTH = (`XLEN-`CLOG2(DATA_SIZE));
localparam ADDR_WIDTH = (`MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE));
localparam DATA_WIDTH = (8 * DATA_SIZE);
localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
localparam TAG_OUT_WIDTH = TAG_WIDTH - LOG_NUM_REQS;