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Icache/Dcache finally done + configurability tested:

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This commit is contained in:
felsabbagh3 2019-11-09 00:03:15 -05:00
parent 8b81989bfd
commit ea7bd485ca
8 changed files with 517 additions and 349 deletions
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2
rtl/VX_define.v
View file

@ -136,7 +136,7 @@
`define ICACHE_WAYS 2
`endif
//Bytes
`define ICACHE_BLOCK 8
`define ICACHE_BLOCK 16
`define ICACHE_BANKS 1
`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS)

15
rtl/cache/VX_Cache_Bank.v vendored
View file

@ -56,8 +56,7 @@ module VX_Cache_Bank
eviction_addr, // What's the eviction tag
data_evicted,
evicted_way,
way_use
evicted_way
);
// localparam NUMBER_BANKS = `CACHE_BANKS;
@ -69,6 +68,8 @@ module VX_Cache_Bank
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
localparam BLOCK_NUM_BITS = `CLOG2(CACHE_BLOCK);
// Inputs
input wire rst;
input wire clk;
@ -94,7 +95,6 @@ module VX_Cache_Bank
input wire[CACHE_WAY_INDEX-1:0] evicted_way;
output wire[CACHE_WAY_INDEX-1:0] way_use;
// Outputs
// Normal shit
@ -122,7 +122,6 @@ module VX_Cache_Bank
wire[CACHE_WAY_INDEX-1:0] update_way;
wire[CACHE_WAY_INDEX-1:0] way_to_update;
assign miss = (tag_use != o_tag) && valid_use && valid_in;
@ -137,8 +136,7 @@ module VX_Cache_Bank
assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
assign update_way = hit ? way_use : 0;
assign eviction_addr = {eviction_tag, actual_index, {(BLOCK_NUM_BITS){1'b0}}}; // Fix with actual data
@ -215,7 +213,7 @@ module VX_Cache_Bank
// assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
assign way_to_update = write_from_mem ? evicted_way : update_way;
assign way_to_update = evicted_way;
end
@ -243,8 +241,7 @@ module VX_Cache_Bank
.tag_use (tag_use),
.data_use (data_use),
.valid_use (valid_use),
.dirty_use (dirty_use),
.way (way_use)
.dirty_use (dirty_use)
);

77
rtl/cache/VX_cache_data_per_index.v vendored
View file

@ -32,8 +32,7 @@ module VX_cache_data_per_index
output wire[TAG_SIZE_END:TAG_SIZE_START] tag_use,
output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
output wire valid_use,
output wire dirty_use,
output wire[CACHE_WAY_INDEX-1:0] way
output wire dirty_use
);
//localparam NUMBER_BANKS = CACHE_BANKS;
@ -46,7 +45,7 @@ module VX_cache_data_per_index
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
// reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
@ -84,26 +83,44 @@ module VX_cache_data_per_index
wire hit = |hit_per_way;
wire miss = ~hit;
wire update = |we && !miss;
wire valid = &valid_use_per_way;
// wire hit = |hit_per_way;
// wire miss = ~hit;
// wire update = |we && !miss;
// wire valid = &valid_use_per_way;
assign way = hit ? way_index : (valid ? eviction_way_index : (invalid_found ? invalid_index : 0));
assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
wire[CACHE_WAY_INDEX-1:0] way_use_Qual;
assign way_use_Qual = (state != CACHE_IDLE) ? way_to_update : way_index;
assign tag_use = tag_use_per_way[way_use_Qual];
assign data_use = data_use_per_way[way_use_Qual];
assign valid_use = valid_use_per_way[way_use_Qual];
assign dirty_use = dirty_use_per_way[way_use_Qual];
// assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
// assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
// assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
// assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
genvar ways;
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0;
assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0;
assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0;
assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
assign write_from_mem_per_way[ways] = evict && (ways == way_use_Qual);
assign we_per_way[ways] = (ways == way_use_Qual) ? (we) : 0;
assign data_write_per_way[ways] = data_write;
// assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0;
// assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? (we) : 0) : 0;
// assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_use_Qual) ? data_write : 0) : 0;
// assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_use_Qual) ? 1 : 0) : 0;
VX_cache_data #(
.NUM_IND (NUM_IND),
@ -128,19 +145,19 @@ module VX_cache_data_per_index
);
end
always @(posedge clk or posedge rst) begin
if (rst) begin
eviction_way_index <= 0;
end else begin
// if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
if((eviction_way_index+1) == CACHE_WAYS) begin
eviction_way_index <= 0;
end else begin
eviction_way_index <= (eviction_way_index + 1);
end
end
end
end
// always @(posedge clk or posedge rst) begin
// if (rst) begin
// eviction_way_index <= 0;
// end else begin
// // if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
// if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
// if((eviction_way_index+1) == CACHE_WAYS) begin
// eviction_way_index <= 0;
// end else begin
// eviction_way_index <= (eviction_way_index + 1);
// end
// end
// end
// end
endmodule

51
rtl/cache/VX_d_cache.v vendored
View file

@ -103,6 +103,8 @@ module VX_d_cache
assign o_p_readdata = new_final_data_read_Qual;
reg[CACHE_WAY_INDEX-1:0] global_way_to_evict;
wire[CACHE_BANKS - 1 : 0][NUM_REQ-1:0] thread_track_banks; // Valid thread mask per bank
wire[CACHE_BANKS - 1 : 0][LOG_NUM_REQ-1:0] index_per_bank; // Index of thread each bank will try to service
@ -116,9 +118,9 @@ module VX_d_cache
reg[CACHE_BANKS-1:0] eviction_wb_old;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_new;
// reg [CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] evicted_way_old;
// wire[CACHE_BANKS -1 : 0][CACHE_WAY_INDEX-1:0] way_used;
// Internal State
reg [3:0] state;
@ -133,7 +135,7 @@ module VX_d_cache
reg[CACHE_BANKS - 1 : 0][31:0] eviction_addr_per_bank;
reg[31:0] miss_addr;
reg[31:0] evict_addr;
// reg[31:0] evict_addr;
wire curr_processor_request_valid = (|i_p_valid);
@ -240,6 +242,9 @@ module VX_d_cache
// Handle if there is more than one miss
assign new_stored_valid = use_valid & (~threads_serviced_Qual);
wire update_global_way_to_evict = ((state == RECIV_MEM_RSP) && (new_state == CACHE_IDLE) && (CACHE_WAYS)) && (CACHE_WAYS > 1);
///////////////////////////////////////////////////////////////////////
genvar cur_t;
integer init_b;
@ -251,28 +256,37 @@ module VX_d_cache
stored_valid <= 0;
// eviction_addr_per_bank <= 0;
miss_addr <= 0;
evict_addr <= 0;
// evict_addr <= 0;
// threads_serviced_Qual = 0;
// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
// begin
// debug_hit_per_bank_mask[init_b] <= 0;
// end
evicted_way_old <= 0;
eviction_wb_old <= 0;
// evicted_way_old <= 0;
// eviction_wb_old <= 0;
global_way_to_evict <= 0;
end else begin
global_way_to_evict <= (update_global_way_to_evict) ? (global_way_to_evict+1) : global_way_to_evict;
state <= new_state;
stored_valid <= new_stored_valid;
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
evict_addr <= eviction_addr_per_bank[miss_bank_index];
if (state == CACHE_IDLE) begin
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
// evict_addr <= eviction_addr_per_bank[miss_bank_index];
end else begin
miss_addr <= 0;
// evict_addr <= 0;
end
end
final_data_read <= new_final_data_read_Qual;
evicted_way_old <= evicted_way_new;
eviction_wb_old <= eviction_wb;
// evicted_way_old <= evicted_way_new;
// eviction_wb_old <= eviction_wb;
end
end
@ -281,13 +295,13 @@ module VX_d_cache
generate
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1)
begin
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? evict_addr :
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? miss_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
i_p_addr[send_index_to_bank[bank_id]];
assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
(state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
0;
// assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] :
// (state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] :
// 0;
wire[1:0] byte_select = bank_addr[1:0];
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START];
@ -344,8 +358,7 @@ module VX_d_cache
.data_evicted (o_m_writedata[bank_id]),
.eviction_wb (eviction_wb[bank_id]), // Something needs to be written back
.fetched_writedata(i_m_readdata[bank_id]), // Data From memory
.evicted_way (evicted_way_new[bank_id]),
.way_use (way_used[bank_id])
.evicted_way (global_way_to_evict)
);
end
@ -354,7 +367,7 @@ module VX_d_cache
// Mem Rsp
// Req to mem:
assign o_m_evict_addr = evict_addr & MEM_ADDR_REQ_MASK;
assign o_m_evict_addr = (eviction_addr_per_bank[0]) & MEM_ADDR_REQ_MASK; // Could be anything because tag+index are same
assign o_m_read_addr = miss_addr & MEM_ADDR_REQ_MASK;
assign o_m_valid = (state == SEND_MEM_REQ);
assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb);

58
runtime/mains/simple/vx_simple_main.c
View file

@ -52,48 +52,48 @@ int main()
// Main is called with all threads active of warp 0
vx_tmc(1);
// vx_print_str("Simple Main\n");
vx_print_str("Simple Main\n");
// // // TMC test
// test_tmc();
// // TMC test
test_tmc();
// // Control Divergence Test
// vx_print_str("test_divergence\n");
// vx_tmc(4);
// test_divergence();
// vx_tmc(1);
// Control Divergence Test
vx_print_str("test_divergence\n");
vx_tmc(4);
test_divergence();
vx_tmc(1);
// Test wspawn
// vx_print_str("test_wspawn\n");
vx_print_str("test_wspawn\n");
test_wsapwn();
// vx_print_str("vx_spawnWarps mat_add_kernel\n");
vx_print_str("vx_spawnWarps mat_add_kernel\n");
// mat_add_args_t arguments;
// arguments.x = x;
// arguments.y = y;
// arguments.z = z;
// arguments.numColums = 4;
// arguments.numRows = 4;
mat_add_args_t arguments;
arguments.x = x;
arguments.y = y;
arguments.z = z;
arguments.numColums = 4;
arguments.numRows = 4;
// int numWarps = 4;
// int numThreads = 4;
int numWarps = 4;
int numThreads = 4;
// vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
// for (int i = 0; i < arguments.numRows; i++)
// {
// for (int j = 0; j < arguments.numColums; j++)
// {
// unsigned index = (i * arguments.numColums) + j;
// vx_print_hex(z[index]);
// vx_print_str(" ");
// }
// vx_print_str("\n");
// }
for (int i = 0; i < arguments.numRows; i++)
{
for (int j = 0; j < arguments.numColums; j++)
{
unsigned index = (i * arguments.numColums) + j;
vx_print_hex(z[index]);
vx_print_str(" ");
}
vx_print_str("\n");
}
return 0;
}

535
runtime/mains/simple/vx_simple_main.dump
View file

@ -114,7 +114,7 @@ Disassembly of section .text:
80000128: 810007b7 lui a5,0x81000
8000012c: fec42703 lw a4,-20(s0)
80000130: 00271713 slli a4,a4,0x2
80000134: 0f878793 addi a5,a5,248 # 810000f8 <z+0xfffffe84>
80000134: 15478793 addi a5,a5,340 # 81000154 <z+0xfffffe84>
80000138: 00f707b3 add a5,a4,a5
8000013c: 0007a783 lw a5,0(a5)
80000140: 00078513 mv a0,a5
@ -137,7 +137,7 @@ Disassembly of section .text:
8000017c: fe842503 lw a0,-24(s0)
80000180: f95ff0ef jal ra,80000114 <vx_print_hex>
80000184: 810007b7 lui a5,0x81000
80000188: 04078513 addi a0,a5,64 # 81000040 <z+0xfffffdcc>
80000188: 04078513 addi a0,a5,64 # 81000040 <z+0xfffffd70>
8000018c: f4dff0ef jal ra,800000d8 <vx_print_str>
80000190: 00000013 nop
80000194: 01c12083 lw ra,28(sp)
@ -151,13 +151,13 @@ Disassembly of section .text:
800001ac: 00812c23 sw s0,24(sp)
800001b0: 02010413 addi s0,sp,32
800001b4: 810007b7 lui a5,0x81000
800001b8: 2507a783 lw a5,592(a5) # 81000250 <z+0xffffffdc>
800001b8: 2ac7a783 lw a5,684(a5) # 810002ac <z+0xffffffdc>
800001bc: 00078513 mv a0,a5
800001c0: ea9ff0ef jal ra,80000068 <vx_tmc>
800001c4: 810007b7 lui a5,0x81000
800001c8: 24c7a703 lw a4,588(a5) # 8100024c <z+0xffffffd8>
800001c8: 2a87a703 lw a4,680(a5) # 810002a8 <z+0xffffffd8>
800001cc: 810007b7 lui a5,0x81000
800001d0: 2487a783 lw a5,584(a5) # 81000248 <z+0xffffffd4>
800001d0: 2a47a783 lw a5,676(a5) # 810002a4 <z+0xffffffd4>
800001d4: 00078513 mv a0,a5
800001d8: 000700e7 jalr a4
800001dc: eadff0ef jal ra,80000088 <vx_warpID>
@ -186,15 +186,15 @@ Disassembly of section .text:
80000230: fed42023 sw a3,-32(s0)
80000234: 810007b7 lui a5,0x81000
80000238: fe442703 lw a4,-28(s0)
8000023c: 24e7a623 sw a4,588(a5) # 8100024c <z+0xffffffd8>
8000023c: 2ae7a423 sw a4,680(a5) # 810002a8 <z+0xffffffd8>
80000240: 810007b7 lui a5,0x81000
80000244: fe042703 lw a4,-32(s0)
80000248: 24e7a423 sw a4,584(a5) # 81000248 <z+0xffffffd4>
80000248: 2ae7a223 sw a4,676(a5) # 810002a4 <z+0xffffffd4>
8000024c: 810007b7 lui a5,0x81000
80000250: fe842703 lw a4,-24(s0)
80000254: 24e7a823 sw a4,592(a5) # 81000250 <z+0xffffffdc>
80000254: 2ae7a623 sw a4,684(a5) # 810002ac <z+0xffffffdc>
80000258: 800007b7 lui a5,0x80000
8000025c: 1a478793 addi a5,a5,420 # 800001a4 <z+0xfeffff30>
8000025c: 1a478793 addi a5,a5,420 # 800001a4 <z+0xfefffed4>
80000260: 00078593 mv a1,a5
80000264: fec42503 lw a0,-20(s0)
80000268: df9ff0ef jal ra,80000060 <vx_wspawn>
@ -211,7 +211,7 @@ Disassembly of section .text:
8000028c: 00812c23 sw s0,24(sp)
80000290: 02010413 addi s0,sp,32
80000294: 810007b7 lui a5,0x81000
80000298: 08478513 addi a0,a5,132 # 81000084 <z+0xfffffe10>
80000298: 08478513 addi a0,a5,132 # 81000084 <z+0xfffffdb4>
8000029c: e3dff0ef jal ra,800000d8 <vx_print_str>
800002a0: 00400513 li a0,4
800002a4: dc5ff0ef jal ra,80000068 <vx_tmc>
@ -221,41 +221,41 @@ Disassembly of section .text:
800002b4: 810007b7 lui a5,0x81000
800002b8: fec42683 lw a3,-20(s0)
800002bc: 00269693 slli a3,a3,0x2
800002c0: 17878793 addi a5,a5,376 # 81000178 <z+0xffffff04>
800002c0: 1d478793 addi a5,a5,468 # 810001d4 <z+0xffffff04>
800002c4: 00f687b3 add a5,a3,a5
800002c8: 00e7a023 sw a4,0(a5)
800002cc: 00100513 li a0,1
800002d0: d99ff0ef jal ra,80000068 <vx_tmc>
800002d4: 810007b7 lui a5,0x81000
800002d8: 1787a783 lw a5,376(a5) # 81000178 <z+0xffffff04>
800002d8: 1d47a783 lw a5,468(a5) # 810001d4 <z+0xffffff04>
800002dc: 00078513 mv a0,a5
800002e0: e35ff0ef jal ra,80000114 <vx_print_hex>
800002e4: 810007b7 lui a5,0x81000
800002e8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800002e8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800002ec: dedff0ef jal ra,800000d8 <vx_print_str>
800002f0: 810007b7 lui a5,0x81000
800002f4: 17878793 addi a5,a5,376 # 81000178 <z+0xffffff04>
800002f4: 1d478793 addi a5,a5,468 # 810001d4 <z+0xffffff04>
800002f8: 0047a783 lw a5,4(a5)
800002fc: 00078513 mv a0,a5
80000300: e15ff0ef jal ra,80000114 <vx_print_hex>
80000304: 810007b7 lui a5,0x81000
80000308: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
80000308: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
8000030c: dcdff0ef jal ra,800000d8 <vx_print_str>
80000310: 810007b7 lui a5,0x81000
80000314: 17878793 addi a5,a5,376 # 81000178 <z+0xffffff04>
80000314: 1d478793 addi a5,a5,468 # 810001d4 <z+0xffffff04>
80000318: 0087a783 lw a5,8(a5)
8000031c: 00078513 mv a0,a5
80000320: df5ff0ef jal ra,80000114 <vx_print_hex>
80000324: 810007b7 lui a5,0x81000
80000328: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
80000328: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
8000032c: dadff0ef jal ra,800000d8 <vx_print_str>
80000330: 810007b7 lui a5,0x81000
80000334: 17878793 addi a5,a5,376 # 81000178 <z+0xffffff04>
80000334: 1d478793 addi a5,a5,468 # 810001d4 <z+0xffffff04>
80000338: 00c7a783 lw a5,12(a5)
8000033c: 00078513 mv a0,a5
80000340: dd5ff0ef jal ra,80000114 <vx_print_hex>
80000344: 810007b7 lui a5,0x81000
80000348: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
80000348: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
8000034c: d8dff0ef jal ra,800000d8 <vx_print_str>
80000350: 00000013 nop
80000354: 01c12083 lw ra,28(sp)
@ -289,7 +289,7 @@ Disassembly of section .text:
800003bc: 810007b7 lui a5,0x81000
800003c0: fec42703 lw a4,-20(s0)
800003c4: 00271713 slli a4,a4,0x2
800003c8: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
800003c8: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
800003cc: 00f707b3 add a5,a4,a5
800003d0: 00a00713 li a4,10
800003d4: 00e7a023 sw a4,0(a5)
@ -297,7 +297,7 @@ Disassembly of section .text:
800003dc: 810007b7 lui a5,0x81000
800003e0: fec42703 lw a4,-20(s0)
800003e4: 00271713 slli a4,a4,0x2
800003e8: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
800003e8: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
800003ec: 00f707b3 add a5,a4,a5
800003f0: 00b00713 li a4,11
800003f4: 00e7a023 sw a4,0(a5)
@ -314,7 +314,7 @@ Disassembly of section .text:
80000420: 810007b7 lui a5,0x81000
80000424: fec42703 lw a4,-20(s0)
80000428: 00271713 slli a4,a4,0x2
8000042c: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
8000042c: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
80000430: 00f707b3 add a5,a4,a5
80000434: 00c00713 li a4,12
80000438: 00e7a023 sw a4,0(a5)
@ -322,42 +322,42 @@ Disassembly of section .text:
80000440: 810007b7 lui a5,0x81000
80000444: fec42703 lw a4,-20(s0)
80000448: 00271713 slli a4,a4,0x2
8000044c: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
8000044c: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
80000450: 00f707b3 add a5,a4,a5
80000454: 00d00713 li a4,13
80000458: 00e7a023 sw a4,0(a5)
8000045c: c25ff0ef jal ra,80000080 <vx_join>
80000460: c21ff0ef jal ra,80000080 <vx_join>
80000464: 810007b7 lui a5,0x81000
80000468: 2647a783 lw a5,612(a5) # 81000264 <z+0xfffffff0>
80000468: 2c07a783 lw a5,704(a5) # 810002c0 <z+0xfffffff0>
8000046c: 00078513 mv a0,a5
80000470: ca5ff0ef jal ra,80000114 <vx_print_hex>
80000474: 810007b7 lui a5,0x81000
80000478: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
80000478: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
8000047c: c5dff0ef jal ra,800000d8 <vx_print_str>
80000480: 810007b7 lui a5,0x81000
80000484: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
80000484: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
80000488: 0047a783 lw a5,4(a5)
8000048c: 00078513 mv a0,a5
80000490: c85ff0ef jal ra,80000114 <vx_print_hex>
80000494: 810007b7 lui a5,0x81000
80000498: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
80000498: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
8000049c: c3dff0ef jal ra,800000d8 <vx_print_str>
800004a0: 810007b7 lui a5,0x81000
800004a4: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
800004a4: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
800004a8: 0087a783 lw a5,8(a5)
800004ac: 00078513 mv a0,a5
800004b0: c65ff0ef jal ra,80000114 <vx_print_hex>
800004b4: 810007b7 lui a5,0x81000
800004b8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800004b8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800004bc: c1dff0ef jal ra,800000d8 <vx_print_str>
800004c0: 810007b7 lui a5,0x81000
800004c4: 26478793 addi a5,a5,612 # 81000264 <z+0xfffffff0>
800004c4: 2c078793 addi a5,a5,704 # 810002c0 <z+0xfffffff0>
800004c8: 00c7a783 lw a5,12(a5)
800004cc: 00078513 mv a0,a5
800004d0: c45ff0ef jal ra,80000114 <vx_print_hex>
800004d4: 810007b7 lui a5,0x81000
800004d8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800004d8: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800004dc: bfdff0ef jal ra,800000d8 <vx_print_str>
800004e0: 00000013 nop
800004e4: 01c12083 lw ra,28(sp)
@ -375,7 +375,7 @@ Disassembly of section .text:
8000050c: 810007b7 lui a5,0x81000
80000510: fec42703 lw a4,-20(s0)
80000514: 00271713 slli a4,a4,0x2
80000518: 25478793 addi a5,a5,596 # 81000254 <z+0xffffffe0>
80000518: 2b078793 addi a5,a5,688 # 810002b0 <z+0xffffffe0>
8000051c: 00f707b3 add a5,a4,a5
80000520: fec42703 lw a4,-20(s0)
80000524: 00e7a023 sw a4,0(a5)
@ -395,42 +395,42 @@ Disassembly of section .text:
80000554: 00812c23 sw s0,24(sp)
80000558: 02010413 addi s0,sp,32
8000055c: 800007b7 lui a5,0x80000
80000560: 4f478793 addi a5,a5,1268 # 800004f4 <z+0xff000280>
80000560: 4f478793 addi a5,a5,1268 # 800004f4 <z+0xff000224>
80000564: fef42623 sw a5,-20(s0)
80000568: fec42583 lw a1,-20(s0)
8000056c: 00400513 li a0,4
80000570: af1ff0ef jal ra,80000060 <vx_wspawn>
80000574: f81ff0ef jal ra,800004f4 <simple_kernel>
80000578: 810007b7 lui a5,0x81000
8000057c: 2547a783 lw a5,596(a5) # 81000254 <z+0xffffffe0>
8000057c: 2b07a783 lw a5,688(a5) # 810002b0 <z+0xffffffe0>
80000580: 00078513 mv a0,a5
80000584: b91ff0ef jal ra,80000114 <vx_print_hex>
80000588: 810007b7 lui a5,0x81000
8000058c: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
8000058c: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
80000590: b49ff0ef jal ra,800000d8 <vx_print_str>
80000594: 810007b7 lui a5,0x81000
80000598: 25478793 addi a5,a5,596 # 81000254 <z+0xffffffe0>
80000598: 2b078793 addi a5,a5,688 # 810002b0 <z+0xffffffe0>
8000059c: 0047a783 lw a5,4(a5)
800005a0: 00078513 mv a0,a5
800005a4: b71ff0ef jal ra,80000114 <vx_print_hex>
800005a8: 810007b7 lui a5,0x81000
800005ac: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800005ac: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800005b0: b29ff0ef jal ra,800000d8 <vx_print_str>
800005b4: 810007b7 lui a5,0x81000
800005b8: 25478793 addi a5,a5,596 # 81000254 <z+0xffffffe0>
800005b8: 2b078793 addi a5,a5,688 # 810002b0 <z+0xffffffe0>
800005bc: 0087a783 lw a5,8(a5)
800005c0: 00078513 mv a0,a5
800005c4: b51ff0ef jal ra,80000114 <vx_print_hex>
800005c8: 810007b7 lui a5,0x81000
800005cc: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800005cc: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800005d0: b09ff0ef jal ra,800000d8 <vx_print_str>
800005d4: 810007b7 lui a5,0x81000
800005d8: 25478793 addi a5,a5,596 # 81000254 <z+0xffffffe0>
800005d8: 2b078793 addi a5,a5,688 # 810002b0 <z+0xffffffe0>
800005dc: 00c7a783 lw a5,12(a5)
800005e0: 00078513 mv a0,a5
800005e4: b31ff0ef jal ra,80000114 <vx_print_hex>
800005e8: 810007b7 lui a5,0x81000
800005ec: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffe20>
800005ec: 09478513 addi a0,a5,148 # 81000094 <z+0xfffffdc4>
800005f0: ae9ff0ef jal ra,800000d8 <vx_print_str>
800005f4: 00000013 nop
800005f8: 01c12083 lw ra,28(sp)
@ -445,7 +445,7 @@ Disassembly of section .text:
80000614: 01010413 addi s0,sp,16
80000618: c6dff0ef jal ra,80000284 <test_tmc>
8000061c: 810007b7 lui a5,0x81000
80000620: 09878513 addi a0,a5,152 # 81000098 <z+0xfffffe24>
80000620: 09878513 addi a0,a5,152 # 81000098 <z+0xfffffdc8>
80000624: ab5ff0ef jal ra,800000d8 <vx_print_str>
80000628: 00400513 li a0,4
8000062c: a3dff0ef jal ra,80000068 <vx_tmc>
@ -453,7 +453,7 @@ Disassembly of section .text:
80000634: 00100513 li a0,1
80000638: a31ff0ef jal ra,80000068 <vx_tmc>
8000063c: 810007b7 lui a5,0x81000
80000640: 0ac78513 addi a0,a5,172 # 810000ac <z+0xfffffe38>
80000640: 0ac78513 addi a0,a5,172 # 810000ac <z+0xfffffddc>
80000644: a95ff0ef jal ra,800000d8 <vx_print_str>
80000648: f05ff0ef jal ra,8000054c <test_wsapwn>
8000064c: 00000013 nop
@ -528,19 +528,98 @@ Disassembly of section .text:
80000758: 00008067 ret
8000075c <main>:
8000075c: ff010113 addi sp,sp,-16
80000760: 00112623 sw ra,12(sp)
80000764: 00812423 sw s0,8(sp)
80000768: 01010413 addi s0,sp,16
8000075c: fc010113 addi sp,sp,-64
80000760: 02112e23 sw ra,60(sp)
80000764: 02812c23 sw s0,56(sp)
80000768: 04010413 addi s0,sp,64
8000076c: 00100513 li a0,1
80000770: 8f9ff0ef jal ra,80000068 <vx_tmc>
80000774: dd9ff0ef jal ra,8000054c <test_wsapwn>
80000778: 00000793 li a5,0
8000077c: 00078513 mv a0,a5
80000780: 00c12083 lw ra,12(sp)
80000784: 00812403 lw s0,8(sp)
80000788: 01010113 addi sp,sp,16
8000078c: 00008067 ret
80000774: 810007b7 lui a5,0x81000
80000778: 0f878513 addi a0,a5,248 # 810000f8 <z+0xfffffe28>
8000077c: 95dff0ef jal ra,800000d8 <vx_print_str>
80000780: b05ff0ef jal ra,80000284 <test_tmc>
80000784: 810007b7 lui a5,0x81000
80000788: 10878513 addi a0,a5,264 # 81000108 <z+0xfffffe38>
8000078c: 94dff0ef jal ra,800000d8 <vx_print_str>
80000790: 00400513 li a0,4
80000794: 8d5ff0ef jal ra,80000068 <vx_tmc>
80000798: bcdff0ef jal ra,80000364 <test_divergence>
8000079c: 00100513 li a0,1
800007a0: 8c9ff0ef jal ra,80000068 <vx_tmc>
800007a4: 810007b7 lui a5,0x81000
800007a8: 11c78513 addi a0,a5,284 # 8100011c <z+0xfffffe4c>
800007ac: 92dff0ef jal ra,800000d8 <vx_print_str>
800007b0: d9dff0ef jal ra,8000054c <test_wsapwn>
800007b4: 810007b7 lui a5,0x81000
800007b8: 12c78513 addi a0,a5,300 # 8100012c <z+0xfffffe5c>
800007bc: 91dff0ef jal ra,800000d8 <vx_print_str>
800007c0: 810007b7 lui a5,0x81000
800007c4: 22478793 addi a5,a5,548 # 81000224 <z+0xffffff54>
800007c8: fcf42423 sw a5,-56(s0)
800007cc: 810007b7 lui a5,0x81000
800007d0: 26478793 addi a5,a5,612 # 81000264 <z+0xffffff94>
800007d4: fcf42623 sw a5,-52(s0)
800007d8: 810007b7 lui a5,0x81000
800007dc: 2d078793 addi a5,a5,720 # 810002d0 <z+0x0>
800007e0: fcf42823 sw a5,-48(s0)
800007e4: 00400793 li a5,4
800007e8: fcf42a23 sw a5,-44(s0)
800007ec: 00400793 li a5,4
800007f0: fcf42c23 sw a5,-40(s0)
800007f4: 00400793 li a5,4
800007f8: fef42223 sw a5,-28(s0)
800007fc: 00400793 li a5,4
80000800: fef42023 sw a5,-32(s0)
80000804: fe442703 lw a4,-28(s0)
80000808: fe042583 lw a1,-32(s0)
8000080c: fc840793 addi a5,s0,-56
80000810: 00078693 mv a3,a5
80000814: 800007b7 lui a5,0x80000
80000818: 66078613 addi a2,a5,1632 # 80000660 <z+0xff000390>
8000081c: 00070513 mv a0,a4
80000820: 9f5ff0ef jal ra,80000214 <vx_spawnWarps>
80000824: fe042623 sw zero,-20(s0)
80000828: 0800006f j 800008a8 <main+0x14c>
8000082c: fe042423 sw zero,-24(s0)
80000830: 0540006f j 80000884 <main+0x128>
80000834: fd442703 lw a4,-44(s0)
80000838: fec42783 lw a5,-20(s0)
8000083c: 02f70733 mul a4,a4,a5
80000840: fe842783 lw a5,-24(s0)
80000844: 00f707b3 add a5,a4,a5
80000848: fcf42e23 sw a5,-36(s0)
8000084c: 810007b7 lui a5,0x81000
80000850: fdc42703 lw a4,-36(s0)
80000854: 00271713 slli a4,a4,0x2
80000858: 2d078793 addi a5,a5,720 # 810002d0 <z+0x0>
8000085c: 00f707b3 add a5,a4,a5
80000860: 0007a783 lw a5,0(a5)
80000864: 00078513 mv a0,a5
80000868: 8adff0ef jal ra,80000114 <vx_print_hex>
8000086c: 810007b7 lui a5,0x81000
80000870: 14c78513 addi a0,a5,332 # 8100014c <z+0xfffffe7c>
80000874: 865ff0ef jal ra,800000d8 <vx_print_str>
80000878: fe842783 lw a5,-24(s0)
8000087c: 00178793 addi a5,a5,1
80000880: fef42423 sw a5,-24(s0)
80000884: fd442703 lw a4,-44(s0)
80000888: fe842783 lw a5,-24(s0)
8000088c: fae7e4e3 bltu a5,a4,80000834 <main+0xd8>
80000890: 810007b7 lui a5,0x81000
80000894: 15078513 addi a0,a5,336 # 81000150 <z+0xfffffe80>
80000898: 841ff0ef jal ra,800000d8 <vx_print_str>
8000089c: fec42783 lw a5,-20(s0)
800008a0: 00178793 addi a5,a5,1
800008a4: fef42623 sw a5,-20(s0)
800008a8: fd842703 lw a4,-40(s0)
800008ac: fec42783 lw a5,-20(s0)
800008b0: f6e7eee3 bltu a5,a4,8000082c <main+0xd0>
800008b4: 00000793 li a5,0
800008b8: 00078513 mv a0,a5
800008bc: 03c12083 lw ra,60(sp)
800008c0: 03812403 lw s0,56(sp)
800008c4: 04010113 addi sp,sp,64
800008c8: 00008067 ret
Disassembly of section .rodata:
@ -652,206 +731,242 @@ Disassembly of section .rodata:
810000f0: 0065 c.nop 25
810000f2: 0000 unimp
810000f4: 0066 c.slli zero,0x19
810000f6: 0000 unimp
810000f8: 706d6953 0x706d6953
810000fc: 656c flw fa1,76(a0)
810000fe: 4d20 lw s0,88(a0)
81000100: 6961 lui s2,0x18
81000102: 0a6e slli s4,s4,0x1b
81000104: 0000 unimp
81000106: 0000 unimp
81000108: 6574 flw fa3,76(a0)
8100010a: 645f7473 csrrci s0,0x645,30
8100010e: 7669 lui a2,0xffffa
81000110: 7265 lui tp,0xffff9
81000112: 636e6567 0x636e6567
81000116: 0a65 addi s4,s4,25
81000118: 0000 unimp
8100011a: 0000 unimp
8100011c: 6574 flw fa3,76(a0)
8100011e: 775f7473 csrrci s0,0x775,30
81000122: 77617073 csrci 0x776,2
81000126: 0a6e slli s4,s4,0x1b
81000128: 0000 unimp
8100012a: 0000 unimp
8100012c: 7876 flw fa6,124(sp)
8100012e: 735f 6170 6e77 0x6e776170735f
81000134: 70726157 0x70726157
81000138: 616d2073 csrs 0x616,s10
8100013c: 5f74 lw a3,124(a4)
8100013e: 6461 lui s0,0x18
81000140: 5f64 lw s1,124(a4)
81000142: 6e72656b 0x6e72656b
81000146: 6c65 lui s8,0x19
81000148: 000a c.slli zero,0x2
8100014a: 0000 unimp
8100014c: 0020 addi s0,sp,8
8100014e: 0000 unimp
81000150: 000a c.slli zero,0x2
Disassembly of section .data:
810000f8 <hextoa>:
810000f8: 0000 unimp
810000fa: 8100 0x8100
810000fc: 0004 0x4
810000fe: 8100 0x8100
81000100: 0008 0x8
81000102: 8100 0x8100
81000104: 000c 0xc
81000106: 8100 0x8100
81000108: 0010 0x10
8100010a: 8100 0x8100
8100010c: 0014 0x14
8100010e: 8100 0x8100
81000110: 0018 0x18
81000112: 8100 0x8100
81000114: 001c 0x1c
81000116: 8100 0x8100
81000118: 0020 addi s0,sp,8
8100011a: 8100 0x8100
8100011c: 0024 addi s1,sp,8
8100011e: 8100 0x8100
81000120: 0028 addi a0,sp,8
81000122: 8100 0x8100
81000124: 002c addi a1,sp,8
81000126: 8100 0x8100
81000128: 0030 addi a2,sp,8
8100012a: 8100 0x8100
8100012c: 0034 addi a3,sp,8
8100012e: 8100 0x8100
81000130: 0038 addi a4,sp,8
81000132: 8100 0x8100
81000134: 003c addi a5,sp,8
81000136: 8100 0x8100
81000138 <hextoa>:
81000138: 0044 addi s1,sp,4
8100013a: 8100 0x8100
8100013c: 0048 addi a0,sp,4
8100013e: 8100 0x8100
81000140: 004c addi a1,sp,4
81000142: 8100 0x8100
81000144: 0050 addi a2,sp,4
81000146: 8100 0x8100
81000148: 0054 addi a3,sp,4
8100014a: 8100 0x8100
8100014c: 0058 addi a4,sp,4
8100014e: 8100 0x8100
81000150: 005c addi a5,sp,4
81000152: 8100 0x8100
81000154: 0060 addi s0,sp,12
81000154 <hextoa>:
81000154: 0000 unimp
81000156: 8100 0x8100
81000158: 0064 addi s1,sp,12
81000158: 0004 0x4
8100015a: 8100 0x8100
8100015c: 0068 addi a0,sp,12
8100015c: 0008 0x8
8100015e: 8100 0x8100
81000160: 006c addi a1,sp,12
81000160: 000c 0xc
81000162: 8100 0x8100
81000164: 0070 addi a2,sp,12
81000164: 0010 0x10
81000166: 8100 0x8100
81000168: 0074 addi a3,sp,12
81000168: 0014 0x14
8100016a: 8100 0x8100
8100016c: 0078 addi a4,sp,12
8100016c: 0018 0x18
8100016e: 8100 0x8100
81000170: 007c addi a5,sp,12
81000170: 001c 0x1c
81000172: 8100 0x8100
81000174: 0080 addi s0,sp,64
81000174: 0020 addi s0,sp,8
81000176: 8100 0x8100
81000178 <tmc_array>:
81000178: 0005 c.nop 1
8100017a: 0000 unimp
8100017c: 0005 c.nop 1
8100017e: 0000 unimp
81000180: 0005 c.nop 1
81000182: 0000 unimp
81000184: 0005 c.nop 1
...
81000188 <hextoa>:
81000188: 00b8 addi a4,sp,72
81000178: 0024 addi s1,sp,8
8100017a: 8100 0x8100
8100017c: 0028 addi a0,sp,8
8100017e: 8100 0x8100
81000180: 002c addi a1,sp,8
81000182: 8100 0x8100
81000184: 0030 addi a2,sp,8
81000186: 8100 0x8100
81000188: 0034 addi a3,sp,8
8100018a: 8100 0x8100
8100018c: 00bc addi a5,sp,72
8100018c: 0038 addi a4,sp,8
8100018e: 8100 0x8100
81000190: 00c0 addi s0,sp,68
81000190: 003c addi a5,sp,8
81000192: 8100 0x8100
81000194: 00c4 addi s1,sp,68
81000196: 8100 0x8100
81000198: 00c8 addi a0,sp,68
8100019a: 8100 0x8100
8100019c: 00cc addi a1,sp,68
8100019e: 8100 0x8100
810001a0: 00d0 addi a2,sp,68
810001a2: 8100 0x8100
810001a4: 00d4 addi a3,sp,68
810001a6: 8100 0x8100
810001a8: 00d8 addi a4,sp,68
810001aa: 8100 0x8100
810001ac: 00dc addi a5,sp,68
810001ae: 8100 0x8100
810001b0: 00e0 addi s0,sp,76
810001b2: 8100 0x8100
810001b4: 00e4 addi s1,sp,76
810001b6: 8100 0x8100
810001b8: 00e8 addi a0,sp,76
810001ba: 8100 0x8100
810001bc: 00ec addi a1,sp,76
810001be: 8100 0x8100
810001c0: 00f0 addi a2,sp,76
810001c2: 8100 0x8100
810001c4: 00f4 addi a3,sp,76
810001c6: 8100 0x8100
810001c8 <x>:
810001c8: 0005 c.nop 1
810001ca: 0000 unimp
810001cc: 0005 c.nop 1
810001ce: 0000 unimp
810001d0: 0005 c.nop 1
810001d2: 0000 unimp
81000194 <hextoa>:
81000194: 0044 addi s1,sp,4
81000196: 8100 0x8100
81000198: 0048 addi a0,sp,4
8100019a: 8100 0x8100
8100019c: 004c addi a1,sp,4
8100019e: 8100 0x8100
810001a0: 0050 addi a2,sp,4
810001a2: 8100 0x8100
810001a4: 0054 addi a3,sp,4
810001a6: 8100 0x8100
810001a8: 0058 addi a4,sp,4
810001aa: 8100 0x8100
810001ac: 005c addi a5,sp,4
810001ae: 8100 0x8100
810001b0: 0060 addi s0,sp,12
810001b2: 8100 0x8100
810001b4: 0064 addi s1,sp,12
810001b6: 8100 0x8100
810001b8: 0068 addi a0,sp,12
810001ba: 8100 0x8100
810001bc: 006c addi a1,sp,12
810001be: 8100 0x8100
810001c0: 0070 addi a2,sp,12
810001c2: 8100 0x8100
810001c4: 0074 addi a3,sp,12
810001c6: 8100 0x8100
810001c8: 0078 addi a4,sp,12
810001ca: 8100 0x8100
810001cc: 007c addi a5,sp,12
810001ce: 8100 0x8100
810001d0: 0080 addi s0,sp,64
810001d2: 8100 0x8100
810001d4 <tmc_array>:
810001d4: 0005 c.nop 1
810001d6: 0000 unimp
810001d8: 0006 c.slli zero,0x1
810001d8: 0005 c.nop 1
810001da: 0000 unimp
810001dc: 0006 c.slli zero,0x1
810001dc: 0005 c.nop 1
810001de: 0000 unimp
810001e0: 0006 c.slli zero,0x1
810001e2: 0000 unimp
810001e4: 0006 c.slli zero,0x1
810001e6: 0000 unimp
810001e8: 00000007 0x7
810001ec: 00000007 0x7
810001f0: 00000007 0x7
810001f4: 00000007 0x7
810001f8: 0008 0x8
810001fa: 0000 unimp
810001fc: 0008 0x8
810001fe: 0000 unimp
81000200: 0008 0x8
81000202: 0000 unimp
81000204: 0008 0x8
810001e0: 0005 c.nop 1
...
81000208 <y>:
81000208: 0001 nop
8100020a: 0000 unimp
8100020c: 0001 nop
8100020e: 0000 unimp
81000210: 0001 nop
81000212: 0000 unimp
81000214: 0001 nop
81000216: 0000 unimp
81000218: 0001 nop
8100021a: 0000 unimp
8100021c: 0001 nop
8100021e: 0000 unimp
81000220: 0001 nop
81000222: 0000 unimp
81000224: 0001 nop
810001e4 <hextoa>:
810001e4: 00b8 addi a4,sp,72
810001e6: 8100 0x8100
810001e8: 00bc addi a5,sp,72
810001ea: 8100 0x8100
810001ec: 00c0 addi s0,sp,68
810001ee: 8100 0x8100
810001f0: 00c4 addi s1,sp,68
810001f2: 8100 0x8100
810001f4: 00c8 addi a0,sp,68
810001f6: 8100 0x8100
810001f8: 00cc addi a1,sp,68
810001fa: 8100 0x8100
810001fc: 00d0 addi a2,sp,68
810001fe: 8100 0x8100
81000200: 00d4 addi a3,sp,68
81000202: 8100 0x8100
81000204: 00d8 addi a4,sp,68
81000206: 8100 0x8100
81000208: 00dc addi a5,sp,68
8100020a: 8100 0x8100
8100020c: 00e0 addi s0,sp,76
8100020e: 8100 0x8100
81000210: 00e4 addi s1,sp,76
81000212: 8100 0x8100
81000214: 00e8 addi a0,sp,76
81000216: 8100 0x8100
81000218: 00ec addi a1,sp,76
8100021a: 8100 0x8100
8100021c: 00f0 addi a2,sp,76
8100021e: 8100 0x8100
81000220: 00f4 addi a3,sp,76
81000222: 8100 0x8100
81000224 <x>:
81000224: 0005 c.nop 1
81000226: 0000 unimp
81000228: 0001 nop
81000228: 0005 c.nop 1
8100022a: 0000 unimp
8100022c: 0001 nop
8100022c: 0005 c.nop 1
8100022e: 0000 unimp
81000230: 0001 nop
81000230: 0005 c.nop 1
81000232: 0000 unimp
81000234: 0001 nop
81000234: 0006 c.slli zero,0x1
81000236: 0000 unimp
81000238: 0001 nop
81000238: 0006 c.slli zero,0x1
8100023a: 0000 unimp
8100023c: 0001 nop
8100023c: 0006 c.slli zero,0x1
8100023e: 0000 unimp
81000240: 0001 nop
81000240: 0006 c.slli zero,0x1
81000242: 0000 unimp
81000244: 0001 nop
81000244: 00000007 0x7
81000248: 00000007 0x7
8100024c: 00000007 0x7
81000250: 00000007 0x7
81000254: 0008 0x8
81000256: 0000 unimp
81000258: 0008 0x8
8100025a: 0000 unimp
8100025c: 0008 0x8
8100025e: 0000 unimp
81000260: 0008 0x8
...
81000264 <y>:
81000264: 0001 nop
81000266: 0000 unimp
81000268: 0001 nop
8100026a: 0000 unimp
8100026c: 0001 nop
8100026e: 0000 unimp
81000270: 0001 nop
81000272: 0000 unimp
81000274: 0001 nop
81000276: 0000 unimp
81000278: 0001 nop
8100027a: 0000 unimp
8100027c: 0001 nop
8100027e: 0000 unimp
81000280: 0001 nop
81000282: 0000 unimp
81000284: 0001 nop
81000286: 0000 unimp
81000288: 0001 nop
8100028a: 0000 unimp
8100028c: 0001 nop
8100028e: 0000 unimp
81000290: 0001 nop
81000292: 0000 unimp
81000294: 0001 nop
81000296: 0000 unimp
81000298: 0001 nop
8100029a: 0000 unimp
8100029c: 0001 nop
8100029e: 0000 unimp
810002a0: 0001 nop
...
Disassembly of section .bss:
81000248 <global_argument_struct>:
81000248: 0000 unimp
810002a4 <global_argument_struct>:
810002a4: 0000 unimp
...
8100024c <global_function_pointer>:
8100024c: 0000 unimp
810002a8 <global_function_pointer>:
810002a8: 0000 unimp
...
81000250 <global_num_threads>:
81000250: 0000 unimp
810002ac <global_num_threads>:
810002ac: 0000 unimp
...
81000254 <wsapwn_arr>:
810002b0 <wsapwn_arr>:
...
81000264 <div_arr>:
810002c0 <div_arr>:
...
81000274 <z>:
810002d0 <z>:
...
Disassembly of section .comment:

BIN
runtime/mains/simple/vx_simple_main.elf
View file

Binary file not shown.

128
runtime/mains/simple/vx_simple_main.hex
View file

@ -18,7 +18,7 @@
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@ -26,31 +26,31 @@
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:1002E000EFF05FE3B707008113854709EFF0DFDE2A
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:1002F000B70700819387471D83A747001385070031
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:10031000B70700819387471D83A7870013850700D0
:10032000EFF05FDFB707008113854709EFF0DFDAF1
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:10034000EFF05FDDB707008113854709EFF0DFD8D5
:10035000130000008320C101032481011301010265
:1003600067800000130101FE232E1100232C810061
@ -59,40 +59,40 @@
:10039000EFF09FCE8347B4FE638407068327C4FE35
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:1003C0000327C4FE131727009387072CB307F700F2
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:1003E0000327C4FE131727009387072CB307F700D2
:1003F0001307B00023A0E700EFF09FC86F0040068E
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:10042000B70700810327C4FE131727009387072C03
:10043000B307F7001307C00023A0E7006F00000216
:10044000B70700810327C4FE1317270093874726A9
:10044000B70700810327C4FE131727009387072CE3
:10045000B307F7001307D00023A0E700EFF05FC257
:10046000EFF01FC2B707008183A747261385070057
:10046000EFF01FC2B707008183A7072C1385070091
:10047000EFF05FCAB707008113854709EFF0DFC5CA
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:10048000B70700819387072C83A7470013850700D0
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:100510000327C4FE131727009387072BB307F700A1
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@ -116,10 +116,30 @@
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@ -136,27 +156,33 @@
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:00000001FF