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tex_unit code refactoring
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2 changed files with 85 additions and 0 deletions
67
hw/rtl/tex_unit/VX_tex_bilerp.v
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67
hw/rtl/tex_unit/VX_tex_bilerp.v
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`include "VX_tex_define.vh"
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module VX_tex_bilerp #(
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parameter CORE_ID = 0
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) (
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input wire [`BLEND_FRAC_64-1:0] blendU,
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input wire [`BLEND_FRAC_64-1:0] blendV,
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input wire [3:0][63:0] texels,
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input wire [`TEX_FORMAT_BITS-1:0] color_enable,
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output wire [31:0] sampled_data
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);
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR(color_enable)
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wire [63:0] UL_lerp;
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wire [63:0] UH_lerp;
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wire [63:0] V_lerp;
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reg [31:0] sampled_r;
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VX_lerp_64 #(
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) UL_lerp (
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.blend(blendU),
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.in_texels({texels[1], texels[0]}),
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.lerp_texel(UL_lerp)
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);
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VX_lerp_64 #(
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) UH_lerp (
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.blend(blendU),
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.in_texels({texels[3], texels[2]}),
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.lerp_texel(UH_lerp)
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);
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VX_lerp_64 #(
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) V_lerp (
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.blend(blendV),
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.in_texels({UH_lerp, UL_lerp}),
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.lerp_texel(V_lerp)
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);
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always @(*) begin
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if (color_enable[3]==1) //R
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sampled_r[31:24] = V_lerp[55:48];
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else
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sampled_r[31:24] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[2]==1) //G
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sampled_r[23:16] = V_lerp[39:32];
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else
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sampled_r[23:16] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[1]==1) //B
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sampled_r[15:8] = V_lerp[23:16];
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else
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sampled_r[15:8] = {`TEX_COLOR_BITS{1'b0}};
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if (color_enable[0]==1) //A
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sampled_r[7:0] = V_lerp[7:0];
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else
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sampled_r[7:0] = {`TEX_COLOR_BITS{1'b1}};
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end
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assign sampled_data = sampled_r;
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endmodule
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18
hw/rtl/tex_unit/VX_tex_lerp.v
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hw/rtl/tex_unit/VX_tex_lerp.v
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`include "VX_tex_define.vh"
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module VX_tex_lerp #(
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) (
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input wire [`BLEND_FRAC_64-1:0] blend,
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input wire [1:0][63:0] in_texels,
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output wire [63:0] lerp_texel
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);
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wire [63:0] lerp_i1;
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wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
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assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
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assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
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assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
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endmodule
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