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Finished FE and BE high-level

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felsabbagh3 2019-09-08 19:28:53 -04:00
parent 981bf0afe5
commit ecf81336db
32 changed files with 1984 additions and 1639 deletions
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117
rtl/VX_back_end.v
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@ -0,0 +1,117 @@
module VX_back_end (
input wire clk,
input wire reset,
input wire fetch_delay,
input wire[31:0] csr_decode_csr_data,
output wire execute_branch_stall,
output wire out_mem_delay,
VX_jal_response_inter VX_jal_rsp,
VX_branch_response_inter VX_branch_rsp,
VX_frE_to_bckE_req_inter VX_bckE_req,
VX_wb_inter VX_writeback_inter,
VX_dcache_response_inter VX_dcache_rsp,
VX_dcache_request_inter VX_dcache_req,
VX_forward_exe_inter VX_fwd_exe,
VX_forward_mem_inter VX_fwd_mem,
VX_forward_wb_inter VX_fwd_wb,
VX_csr_write_request_inter VX_csr_w_req
);
wire memory_delay;
assign out_mem_delay = memory_delay;
wire total_freeze = fetch_delay || memory_delay;
wire[11:0] execute_csr_address;
wire execute_is_csr;
reg[31:0] execute_csr_result;
wire execute_jal;
wire[31:0] execute_jal_dest;
VX_mw_wb_inter VX_mw_wb();
VX_mem_req_inter VX_exe_mem_req();
VX_mem_req_inter VX_mem_req();
VX_inst_mem_wb_inter VX_mem_wb();
VX_execute vx_execute(
.VX_bckE_req (VX_bckE_req),
.VX_fwd_exe (VX_fwd_exe),
.in_csr_data (csr_decode_csr_data),
.VX_exe_mem_req (VX_exe_mem_req),
.out_csr_address (execute_csr_address),
.out_is_csr (execute_is_csr),
.out_csr_result (execute_csr_result),
.out_jal (execute_jal),
.out_jal_dest (execute_jal_dest),
.out_branch_stall (execute_branch_stall)
);
assign VX_jal_rsp.jal_warp_num = VX_mem_req.warp_num;
VX_e_m_reg vx_e_m_reg(
.clk (clk),
.reset (reset),
.in_csr_address (execute_csr_address),
.in_is_csr (execute_is_csr),
.in_csr_result (execute_csr_result),
.in_jal (execute_jal),
.in_jal_dest (execute_jal_dest),
.in_freeze (total_freeze),
.VX_exe_mem_req (VX_exe_mem_req),
.VX_mem_req (VX_mem_req),
.out_csr_address (VX_csr_w_req.csr_address),
.out_is_csr (VX_csr_w_req.is_csr),
.out_csr_result (VX_csr_w_req.csr_result),
.out_jal (VX_jal_rsp.jal),
.out_jal_dest (VX_jal_rsp.jal_dest)
);
VX_memory vx_memory(
.VX_mem_req (VX_mem_req),
.VX_mem_wb (VX_mem_wb),
.VX_fwd_mem (VX_fwd_mem),
.out_delay (memory_delay),
.VX_branch_rsp (VX_branch_rsp),
.VX_dcache_rsp(VX_dcache_rsp),
.VX_dcache_req (VX_dcache_req)
);
VX_m_w_reg vx_m_w_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.VX_mem_wb (VX_mem_wb),
.VX_mw_wb (VX_mw_wb)
);
VX_writeback vx_writeback(
.VX_mw_wb (VX_mw_wb),
.VX_fwd_wb (VX_fwd_wb),
.VX_writeback_inter(VX_writeback_inter)
);
endmodule

17
rtl/VX_csr_handler.v
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@ -3,15 +3,22 @@
module VX_csr_handler (
input wire clk,
input wire[11:0] in_decode_csr_address, // done
input wire[11:0] in_mem_csr_address,
input wire in_mem_is_csr,
/* verilator lint_off UNUSED */
input wire[31:0] in_mem_csr_result,
/* verilator lint_on UNUSED */
VX_csr_write_request_inter VX_csr_w_req,
input wire in_wb_valid,
output wire[31:0] out_decode_csr_data // done
);
wire in_mem_is_csr;
wire[11:0] in_mem_csr_address;
/* verilator lint_off UNUSED */
wire[31:0] in_mem_csr_result;
/* verilator lint_on UNUSED */
assign in_mem_is_csr = VX_csr_w_req.is_csr;
assign in_mem_csr_address = VX_csr_w_req.csr_address;
assign in_mem_csr_result = VX_csr_w_req.csr_result;
reg[1024:0][11:0] csr;
reg[63:0] cycle;

21
rtl/VX_memory.v
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@ -14,29 +14,26 @@ module VX_memory (
VX_branch_response_inter VX_branch_rsp,
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read,
output wire[2:0] out_cache_driver_in_mem_write,
output wire out_cache_driver_in_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
VX_dcache_response_inter VX_dcache_rsp,
VX_dcache_request_inter VX_dcache_req
);
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) begin
assign out_cache_driver_in_address[index] = VX_mem_req.alu_result[index];
assign out_cache_driver_in_data[index] = VX_mem_req.rd2[index];
assign out_cache_driver_in_valid[index] = VX_mem_req.valid[index];
assign VX_dcache_req.out_cache_driver_in_address[index] = VX_mem_req.alu_result[index];
assign VX_dcache_req.out_cache_driver_in_data[index] = VX_mem_req.rd2[index];
assign VX_dcache_req.out_cache_driver_in_valid[index] = VX_mem_req.valid[index];
assign VX_mem_wb.mem_result[index] = in_cache_driver_out_data[index];
assign VX_mem_wb.mem_result[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
end
assign out_delay = 1'b0;
assign out_cache_driver_in_mem_read = VX_mem_req.mem_read;
assign out_cache_driver_in_mem_write = VX_mem_req.mem_write;
assign VX_dcache_req.out_cache_driver_in_mem_read = VX_mem_req.mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = VX_mem_req.mem_write;
assign VX_mem_wb.alu_result = VX_mem_req.alu_result;

202
rtl/Vortex.v
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@ -15,81 +15,63 @@ module Vortex(
output wire out_ebreak
);
wire[11:0] decode_csr_address;
// From fetch
wire fetch_delay;
wire fetch_ebreak;
// From execute
wire execute_branch_stall;
wire[11:0] execute_csr_address;
wire execute_is_csr;
reg[31:0] execute_csr_result;
wire execute_jal;
wire[31:0] execute_jal_dest;
// Dcache Interface
VX_dcache_response_inter VX_dcache_rsp();
VX_dcache_request_inter VX_dcache_req();
assign out_cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
assign out_cache_driver_in_mem_read = VX_dcache_req.out_cache_driver_in_mem_read;
assign out_cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
assign out_cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid;
assign out_cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
assign VX_dcache_rsp.in_cache_driver_out_data = in_cache_driver_out_data;
// From e_m_register
wire e_m_jal;
wire[31:0] e_m_jal_dest;
wire[11:0] e_m_csr_address;
wire e_m_is_csr;
wire[31:0] e_m_csr_result;
// From memory
wire memory_delay;
// From csr handler
wire[31:0] csr_decode_csr_data;
// From forwarding
wire forwarding_fwd_stall;
// Internal
wire total_freeze;
assign total_freeze = fetch_delay || memory_delay;
assign out_ebreak = fetch_ebreak;
VX_inst_meta_inter fd_inst_meta_de();
VX_frE_to_bckE_req_inter VX_bckE_req();
VX_mem_req_inter VX_exe_mem_req();
VX_mem_req_inter VX_mem_req();
VX_inst_mem_wb_inter VX_mem_wb();
VX_mw_wb_inter VX_mw_wb();
VX_wb_inter VX_writeback_inter();
VX_forward_reqeust_inter VX_fwd_req_de();
VX_forward_exe_inter VX_fwd_exe();
VX_forward_mem_inter VX_fwd_mem();
VX_forward_wb_inter VX_fwd_wb();
VX_forward_response_inter VX_fwd_rsp();
// Icache Interface
VX_icache_response_inter icache_response_fe();
VX_icache_request_inter icache_request_fe();
VX_branch_response_inter VX_branch_rsp();
VX_jal_response_inter VX_jal_rsp();
assign icache_response_fe.instruction = icache_response_instruction;
assign icache_request_pc_address = icache_request_fe.pc_address;
/////////////////////////////////////////////////////////////////////////
// Front-end to Back-end
VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
wire fetch_delay;
// Back-end to Front-end
VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
wire execute_branch_stall;
wire memory_delay;
// Forwarding Buses
VX_forward_reqeust_inter VX_fwd_req_de(); // Forward request
VX_forward_response_inter VX_fwd_rsp(); // Forward Response
VX_forward_exe_inter VX_fwd_exe(); // Data available in EXE
VX_forward_mem_inter VX_fwd_mem(); // Data available in MEM
VX_forward_wb_inter VX_fwd_wb(); // Data available in WB
wire forwarding_fwd_stall;
// CSR Buses
VX_csr_write_request_inter VX_csr_w_req();
wire[31:0] csr_decode_csr_data;
wire[11:0] decode_csr_address;
VX_front_end vx_front_end(
.clk (clk),
@ -107,77 +89,27 @@ VX_front_end vx_front_end(
.icache_request_fe (icache_request_fe),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.fetch_ebreak (fetch_ebreak)
.fetch_ebreak (out_ebreak)
);
VX_execute vx_execute(
.VX_bckE_req (VX_bckE_req),
.VX_fwd_exe (VX_fwd_exe),
.in_csr_data (csr_decode_csr_data),
.VX_exe_mem_req (VX_exe_mem_req),
.out_csr_address (execute_csr_address),
.out_is_csr (execute_is_csr),
.out_csr_result (execute_csr_result),
.out_jal (execute_jal),
.out_jal_dest (execute_jal_dest),
.out_branch_stall (execute_branch_stall)
);
assign VX_jal_rsp.jal = e_m_jal;
assign VX_jal_rsp.jal_dest = e_m_jal_dest;
assign VX_jal_rsp.jal_warp_num = VX_mem_req.warp_num;
VX_e_m_reg vx_e_m_reg(
.clk (clk),
.reset (reset),
.in_csr_address (execute_csr_address),
.in_is_csr (execute_is_csr),
.in_csr_result (execute_csr_result),
.in_jal (execute_jal),
.in_jal_dest (execute_jal_dest),
.in_freeze (total_freeze),
.VX_exe_mem_req (VX_exe_mem_req),
.VX_mem_req (VX_mem_req),
.out_csr_address (e_m_csr_address),
.out_is_csr (e_m_is_csr),
.out_csr_result (e_m_csr_result),
.out_jal (e_m_jal),
.out_jal_dest (e_m_jal_dest)
);
VX_memory vx_memory(
.VX_mem_req (VX_mem_req),
.VX_mem_wb (VX_mem_wb),
.VX_fwd_mem (VX_fwd_mem),
.out_delay (memory_delay),
.VX_branch_rsp (VX_branch_rsp),
.in_cache_driver_out_data (in_cache_driver_out_data),
.out_cache_driver_in_address (out_cache_driver_in_address),
.out_cache_driver_in_mem_read (out_cache_driver_in_mem_read),
.out_cache_driver_in_mem_write(out_cache_driver_in_mem_write),
.out_cache_driver_in_data (out_cache_driver_in_data),
.out_cache_driver_in_valid (out_cache_driver_in_valid)
);
VX_m_w_reg vx_m_w_reg(
.clk (clk),
.reset (reset),
.in_freeze (total_freeze),
.VX_mem_wb (VX_mem_wb),
.VX_mw_wb (VX_mw_wb)
);
VX_writeback vx_writeback(
.VX_mw_wb (VX_mw_wb),
.VX_fwd_wb (VX_fwd_wb),
.VX_writeback_inter(VX_writeback_inter)
VX_back_end vx_back_end(
.clk (clk),
.reset (reset),
.fetch_delay (fetch_delay),
.VX_bckE_req (VX_bckE_req),
.VX_fwd_exe (VX_fwd_exe),
.csr_decode_csr_data (csr_decode_csr_data),
.execute_branch_stall(execute_branch_stall),
.VX_jal_rsp (VX_jal_rsp),
.VX_branch_rsp (VX_branch_rsp),
.VX_dcache_rsp (VX_dcache_rsp),
.VX_dcache_req (VX_dcache_req),
.VX_fwd_mem (VX_fwd_mem),
.VX_fwd_wb (VX_fwd_wb),
.VX_csr_w_req (VX_csr_w_req),
.VX_writeback_inter (VX_writeback_inter),
.out_mem_delay (memory_delay)
);
VX_forwarding vx_forwarding(
@ -192,10 +124,8 @@ VX_forwarding vx_forwarding(
VX_csr_handler vx_csr_handler(
.clk (clk),
.in_decode_csr_address(decode_csr_address),
.in_mem_csr_address (e_m_csr_address),
.in_mem_is_csr (e_m_is_csr),
.in_mem_csr_result (e_m_csr_result),
.in_wb_valid (VX_mw_wb.valid[0]),
.VX_csr_w_req (VX_csr_w_req),
.in_wb_valid (VX_writeback_inter.wb_valid[0]),
.out_decode_csr_data (csr_decode_csr_data)
);

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rtl/interfaces/._VX_csr_write_request_inter.v Normal file
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rtl/interfaces/._VX_dcache_request_inter.v Normal file
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rtl/interfaces/._VX_dcache_response_inter.v Normal file
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35
rtl/interfaces/VX_csr_write_request_inter.v Normal file
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@ -0,0 +1,35 @@
`include "VX_define.v"
`ifndef VX_CSR_W_REQ
`define VX_CSR_W_REQ
interface VX_csr_write_request_inter ();
wire is_csr;
wire[11:0] csr_address;
/* verilator lint_off UNUSED */
wire[31:0] csr_result;
/* verilator lint_on UNUSED */
// source-side view
modport snk (
input is_csr,
input csr_address,
input csr_result
);
// source-side view
modport src (
output is_csr,
output csr_address,
output csr_result
);
endinterface
`endif

39
rtl/interfaces/VX_dcache_request_inter.v Normal file
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@ -0,0 +1,39 @@
`include "VX_define.v"
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
interface VX_dcache_request_inter ();
wire[31:0] out_cache_driver_in_address[`NT_M1:0];
wire[2:0] out_cache_driver_in_mem_read;
wire[2:0] out_cache_driver_in_mem_write;
wire out_cache_driver_in_valid[`NT_M1:0];
wire[31:0] out_cache_driver_in_data[`NT_M1:0];
// source-side view
modport snk (
input out_cache_driver_in_address,
input out_cache_driver_in_mem_read,
input out_cache_driver_in_mem_write,
input out_cache_driver_in_valid,
input out_cache_driver_in_data
);
// source-side view
modport src (
output out_cache_driver_in_address,
output out_cache_driver_in_mem_read,
output out_cache_driver_in_mem_write,
output out_cache_driver_in_valid,
output out_cache_driver_in_data
);
endinterface
`endif

27
rtl/interfaces/VX_dcache_response_inter.v Normal file
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@ -0,0 +1,27 @@
`include "VX_define.v"
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
interface VX_dcache_response_inter ();
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
// source-side view
modport snk (
input in_cache_driver_out_data
);
// source-side view
modport src (
output in_cache_driver_out_data
);
endinterface
`endif

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rtl/obj_dir/VVortex
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2785
rtl/obj_dir/VVortex.cpp
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55
rtl/obj_dir/VVortex.h
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@ -11,13 +11,15 @@
#include "verilated.h"
class VVortex__Syms;
class VVortex_VX_inst_meta_inter;
class VVortex_VX_dcache_response_inter;
class VVortex_VX_dcache_request_inter;
class VVortex_VX_frE_to_bckE_req_inter;
class VVortex_VX_mem_req_inter;
class VVortex_VX_inst_mem_wb_inter;
class VVortex_VX_wb_inter;
class VVortex_VX_branch_response_inter;
class VVortex_VX_warp_ctl_inter;
class VVortex_VX_inst_meta_inter;
class VVortex_VX_mem_req_inter;
class VVortex_VX_inst_mem_wb_inter;
//----------
@ -26,17 +28,18 @@ VL_MODULE(VVortex) {
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__fd_inst_meta_de;
VVortex_VX_dcache_response_inter* __PVT__Vortex__DOT__VX_dcache_rsp;
VVortex_VX_dcache_request_inter* __PVT__Vortex__DOT__VX_dcache_req;
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__VX_bckE_req;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__VX_exe_mem_req;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__VX_mem_req;
VVortex_VX_inst_mem_wb_inter* __PVT__Vortex__DOT__VX_mem_wb;
VVortex_VX_wb_inter* __PVT__Vortex__DOT__VX_writeback_inter;
VVortex_VX_branch_response_inter* __PVT__Vortex__DOT__VX_branch_rsp;
VVortex_VX_warp_ctl_inter* __PVT__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__vx_front_end__DOT__fd_inst_meta_de;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_req;
VVortex_VX_inst_mem_wb_inter* __PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
// PORTS
// The application code writes and reads these signals to
@ -130,7 +133,7 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_back_end__DOT__vx_memory__DOT__temp_branch_dir,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
@ -217,22 +220,22 @@ VL_MODULE(VVortex) {
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,463,0,15);
VL_SIGW(Vortex__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,302,0,10);
VL_SIGW(Vortex__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,463,0,15);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,302,0,10);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src1_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__out_src2_fwd_data,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next,127,0,4);
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next,127,0,4);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT__in_thread_mask[4],0,0);
@ -353,15 +356,11 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIGW(Vortex__DOT__vx_front_end__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_back_end__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIGW(Vortex__DOT__vx_back_end__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,463,0,15);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
VL_SIG8(Vortex__DOT__vx_front_end__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);

44
rtl/obj_dir/VVortex_VX_dcache_request_inter.cpp Normal file
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@ -0,0 +1,44 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_dcache_request_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_dcache_request_inter::~VVortex_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_dcache_request_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_dcache_request_inter::_ctor_var_reset\n"); );
// Body
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
}}
}

49
rtl/obj_dir/VVortex_VX_dcache_request_inter.h Normal file
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@ -0,0 +1,49 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_dcache_request_inter_H_
#define _VVortex_VX_dcache_request_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_dcache_request_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG(out_cache_driver_in_address[4],31,0);
VL_SIG8(out_cache_driver_in_valid[4],0,0);
VL_SIG(out_cache_driver_in_data[4],31,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_dcache_request_inter); ///< Copying not allowed
public:
VVortex_VX_dcache_request_inter(const char* name="TOP");
~VVortex_VX_dcache_request_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

38
rtl/obj_dir/VVortex_VX_dcache_response_inter.cpp Normal file
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@ -0,0 +1,38 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVortex.h for the primary calling header
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVortex_VX_dcache_response_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVortex_VX_dcache_response_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVortex_VX_dcache_response_inter::~VVortex_VX_dcache_response_inter() {
}
//--------------------
// Internal Methods
void VVortex_VX_dcache_response_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_dcache_response_inter::_ctor_var_reset\n"); );
// Body
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
}}
}

47
rtl/obj_dir/VVortex_VX_dcache_response_inter.h Normal file
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@ -0,0 +1,47 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VVortex.h for the primary calling header
#ifndef _VVortex_VX_dcache_response_inter_H_
#define _VVortex_VX_dcache_response_inter_H_
#include "verilated.h"
class VVortex__Syms;
//----------
VL_MODULE(VVortex_VX_dcache_response_inter) {
public:
// PORTS
// LOCAL SIGNALS
// Begin mtask footprint all:
VL_SIG(in_cache_driver_out_data[4],31,0);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
VVortex__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVortex_VX_dcache_response_inter); ///< Copying not allowed
public:
VVortex_VX_dcache_response_inter(const char* name="TOP");
~VVortex_VX_dcache_response_inter();
// API METHODS
// INTERNAL METHODS
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
void _ctor_var_reset() VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

2
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.cpp
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@ -30,7 +30,7 @@ VVortex_VX_inst_mem_wb_inter::~VVortex_VX_inst_mem_wb_inter() {
// Internal Methods
void VVortex_VX_inst_mem_wb_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_mem_wb_inter::_ctor_var_reset\n"); );
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_mem_wb_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,mem_result);
}

2
rtl/obj_dir/VVortex_VX_mem_req_inter.cpp
View file

@ -30,7 +30,7 @@ VVortex_VX_mem_req_inter::~VVortex_VX_mem_req_inter() {
// Internal Methods
void VVortex_VX_mem_req_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_mem_req_inter::_ctor_var_reset\n"); );
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_mem_req_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,alu_result);
wb = VL_RAND_RESET_I(2);

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8
rtl/obj_dir/VVortex__ALLcls.cpp
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@ -1,10 +1,12 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVortex.cpp"
#include "VVortex_VX_mem_req_inter.cpp"
#include "VVortex_VX_inst_mem_wb_inter.cpp"
#include "VVortex_VX_inst_meta_inter.cpp"
#include "VVortex_VX_dcache_response_inter.cpp"
#include "VVortex_VX_dcache_request_inter.cpp"
#include "VVortex_VX_frE_to_bckE_req_inter.cpp"
#include "VVortex_VX_wb_inter.cpp"
#include "VVortex_VX_branch_response_inter.cpp"
#include "VVortex_VX_warp_ctl_inter.cpp"
#include "VVortex_VX_inst_meta_inter.cpp"
#include "VVortex_VX_mem_req_inter.cpp"
#include "VVortex_VX_inst_mem_wb_inter.cpp"

16
rtl/obj_dir/VVortex__ALLcls.d
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@ -1,10 +1,12 @@
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h \
VVortex_VX_mem_req_inter.h VVortex_VX_inst_mem_wb_inter.h \
VVortex_VX_inst_meta_inter.h VVortex_VX_frE_to_bckE_req_inter.h \
VVortex_VX_wb_inter.h VVortex_VX_branch_response_inter.h \
VVortex_VX_warp_ctl_inter.h VVortex_VX_mem_req_inter.cpp \
VVortex_VX_inst_mem_wb_inter.cpp VVortex_VX_inst_meta_inter.cpp \
VVortex_VX_frE_to_bckE_req_inter.cpp VVortex_VX_wb_inter.cpp \
VVortex_VX_branch_response_inter.cpp VVortex_VX_warp_ctl_inter.cpp
VVortex_VX_dcache_response_inter.h VVortex_VX_dcache_request_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_wb_inter.h \
VVortex_VX_branch_response_inter.h VVortex_VX_warp_ctl_inter.h \
VVortex_VX_inst_meta_inter.h VVortex_VX_mem_req_inter.h \
VVortex_VX_inst_mem_wb_inter.h VVortex_VX_dcache_response_inter.cpp \
VVortex_VX_dcache_request_inter.cpp VVortex_VX_frE_to_bckE_req_inter.cpp \
VVortex_VX_wb_inter.cpp VVortex_VX_branch_response_inter.cpp \
VVortex_VX_warp_ctl_inter.cpp VVortex_VX_inst_meta_inter.cpp \
VVortex_VX_mem_req_inter.cpp VVortex_VX_inst_mem_wb_inter.cpp

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9
rtl/obj_dir/VVortex__ALLsup.d
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@ -1,7 +1,8 @@
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVortex.h \
VVortex_VX_mem_req_inter.h VVortex_VX_inst_mem_wb_inter.h \
VVortex_VX_inst_meta_inter.h VVortex_VX_frE_to_bckE_req_inter.h \
VVortex_VX_wb_inter.h VVortex_VX_branch_response_inter.h \
VVortex_VX_warp_ctl_inter.h
VVortex_VX_dcache_response_inter.h VVortex_VX_dcache_request_inter.h \
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_wb_inter.h \
VVortex_VX_branch_response_inter.h VVortex_VX_warp_ctl_inter.h \
VVortex_VX_inst_meta_inter.h VVortex_VX_mem_req_inter.h \
VVortex_VX_inst_mem_wb_inter.h

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26
rtl/obj_dir/VVortex__Syms.cpp
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@ -3,13 +3,15 @@
#include "VVortex__Syms.h"
#include "VVortex.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex_VX_frE_to_bckE_req_inter.h"
#include "VVortex_VX_wb_inter.h"
#include "VVortex_VX_branch_response_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
// FUNCTIONS
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
@ -18,9 +20,11 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
, __Vm_didInit(false)
// Setup submodule names
, TOP__Vortex__DOT__VX_branch_rsp (Verilated::catName(topp->name(),"Vortex.VX_branch_rsp"))
, TOP__Vortex__DOT__VX_exe_mem_req (Verilated::catName(topp->name(),"Vortex.VX_exe_mem_req"))
, TOP__Vortex__DOT__VX_mem_wb (Verilated::catName(topp->name(),"Vortex.VX_mem_wb"))
, TOP__Vortex__DOT__VX_dcache_req (Verilated::catName(topp->name(),"Vortex.VX_dcache_req"))
, TOP__Vortex__DOT__VX_dcache_rsp (Verilated::catName(topp->name(),"Vortex.VX_dcache_rsp"))
, TOP__Vortex__DOT__VX_writeback_inter (Verilated::catName(topp->name(),"Vortex.VX_writeback_inter"))
, TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req (Verilated::catName(topp->name(),"Vortex.vx_back_end.VX_exe_mem_req"))
, TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb (Verilated::catName(topp->name(),"Vortex.vx_back_end.VX_mem_wb"))
, TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req (Verilated::catName(topp->name(),"Vortex.vx_front_end.VX_frE_to_bckE_req"))
, TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl (Verilated::catName(topp->name(),"Vortex.vx_front_end.VX_warp_ctl"))
, TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd (Verilated::catName(topp->name(),"Vortex.vx_front_end.fe_inst_meta_fd"))
@ -29,18 +33,22 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__Vortex__DOT__VX_branch_rsp = &TOP__Vortex__DOT__VX_branch_rsp;
TOPp->__PVT__Vortex__DOT__VX_exe_mem_req = &TOP__Vortex__DOT__VX_exe_mem_req;
TOPp->__PVT__Vortex__DOT__VX_mem_wb = &TOP__Vortex__DOT__VX_mem_wb;
TOPp->__PVT__Vortex__DOT__VX_dcache_req = &TOP__Vortex__DOT__VX_dcache_req;
TOPp->__PVT__Vortex__DOT__VX_dcache_rsp = &TOP__Vortex__DOT__VX_dcache_rsp;
TOPp->__PVT__Vortex__DOT__VX_writeback_inter = &TOP__Vortex__DOT__VX_writeback_inter;
TOPp->__PVT__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req = &TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
TOPp->__PVT__Vortex__DOT__vx_back_end__DOT__VX_mem_wb = &TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req = &TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl = &TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
TOPp->__PVT__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd = &TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__Vortex__DOT__VX_branch_rsp.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_exe_mem_req.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_mem_wb.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_dcache_rsp.__Vconfigure(this, true);
TOP__Vortex__DOT__VX_writeback_inter.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl.__Vconfigure(this, true);
TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd.__Vconfigure(this, true);

14
rtl/obj_dir/VVortex__Syms.h
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@ -11,13 +11,15 @@
// INCLUDE MODULE CLASSES
#include "VVortex.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_dcache_response_inter.h"
#include "VVortex_VX_dcache_request_inter.h"
#include "VVortex_VX_frE_to_bckE_req_inter.h"
#include "VVortex_VX_wb_inter.h"
#include "VVortex_VX_branch_response_inter.h"
#include "VVortex_VX_warp_ctl_inter.h"
#include "VVortex_VX_inst_meta_inter.h"
#include "VVortex_VX_mem_req_inter.h"
#include "VVortex_VX_inst_mem_wb_inter.h"
// SYMS CLASS
class VVortex__Syms : public VerilatedSyms {
@ -30,9 +32,11 @@ class VVortex__Syms : public VerilatedSyms {
// SUBCELL STATE
VVortex* TOPp;
VVortex_VX_branch_response_inter TOP__Vortex__DOT__VX_branch_rsp;
VVortex_VX_mem_req_inter TOP__Vortex__DOT__VX_exe_mem_req;
VVortex_VX_inst_mem_wb_inter TOP__Vortex__DOT__VX_mem_wb;
VVortex_VX_dcache_request_inter TOP__Vortex__DOT__VX_dcache_req;
VVortex_VX_dcache_response_inter TOP__Vortex__DOT__VX_dcache_rsp;
VVortex_VX_wb_inter TOP__Vortex__DOT__VX_writeback_inter;
VVortex_VX_mem_req_inter TOP__Vortex__DOT__vx_back_end__DOT__VX_exe_mem_req;
VVortex_VX_inst_mem_wb_inter TOP__Vortex__DOT__vx_back_end__DOT__VX_mem_wb;
VVortex_VX_frE_to_bckE_req_inter TOP__Vortex__DOT__vx_front_end__DOT__VX_frE_to_bckE_req;
VVortex_VX_warp_ctl_inter TOP__Vortex__DOT__vx_front_end__DOT__VX_warp_ctl;
VVortex_VX_inst_meta_inter TOP__Vortex__DOT__vx_front_end__DOT__fe_inst_meta_fd;

2
rtl/obj_dir/VVortex__ver.d
View file

@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v interfaces//VX_branch_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_branch_response_inter.cpp obj_dir/VVortex_VX_branch_response_inter.h obj_dir/VVortex_VX_dcache_request_inter.cpp obj_dir/VVortex_VX_dcache_request_inter.h obj_dir/VVortex_VX_dcache_response_inter.cpp obj_dir/VVortex_VX_dcache_response_inter.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_back_end.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_decode.v VX_define.v VX_execute.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v interfaces//VX_branch_response_inter.v interfaces//VX_csr_write_request_inter.v interfaces//VX_dcache_request_inter.v interfaces//VX_dcache_response_inter.v interfaces//VX_forward_exe_inter.v interfaces//VX_forward_mem_inter.sv interfaces//VX_forward_reqeust_inter.v interfaces//VX_forward_response_inter.v interfaces//VX_forward_wb_inter.v interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_icache_request_inter.v interfaces//VX_icache_response_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_jal_response_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_mw_wb_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v pipe_regs//VX_d_e_reg.v pipe_regs//VX_e_m_reg.v pipe_regs//VX_f_d_reg.v pipe_regs//VX_m_w_reg.v

58
rtl/obj_dir/VVortex__verFiles.dat
View file

@ -2,9 +2,10 @@
C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
S 2767 1703128 1567984522 0 1567984522 0 "VX_back_end.v"
S 3553 1572595 1567702966 0 1567702966 0 "VX_context.v"
S 4995 1572594 1567702948 0 1567702948 0 "VX_context_slave.v"
S 1650 1701571 1567981832 0 1567981832 0 "VX_csr_handler.v"
S 1837 1768199 1567984564 0 1567984564 0 "VX_csr_handler.v"
S 17085 1574349 1567973680 0 1567973680 0 "VX_decode.v"
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
S 3835 1573272 1567973378 0 1567973378 0 "VX_execute.v"
@ -12,14 +13,17 @@ S 6520 1598760 1567980382 0 1567980382 0 "VX_fetch.v
S 6148 1701713 1567982096 0 1567982096 0 "VX_forwarding.v"
S 2719 1701603 1567981038 0 1567981038 0 "VX_front_end.v"
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
S 2746 1610915 1567979674 0 1567979674 0 "VX_memory.v"
S 2584 1768087 1567983338 0 1567983338 0 "VX_memory.v"
S 1249 1572596 1567702894 0 1567702894 0 "VX_register_file.v"
S 1655 1572598 1567702916 0 1567702916 0 "VX_register_file_master_slave.v"
S 1599 1572597 1567702888 0 1567702888 0 "VX_register_file_slave.v"
S 1915 1565256 1567474434 0 1567474434 0 "VX_warp.v"
S 1597 1704649 1567981924 0 1567981924 0 "VX_writeback.v"
S 5502 1701604 1567981052 0 1567981052 0 "Vortex.v"
S 4392 1703129 1567985238 0 1567985238 0 "Vortex.v"
S 389 1610834 1567980040 0 1567980040 0 "interfaces//VX_branch_response_inter.v"
S 474 1768191 1567983792 0 1567983792 0 "interfaces//VX_csr_write_request_inter.v"
S 823 1703164 1567983106 0 1567983106 0 "interfaces//VX_dcache_request_inter.v"
S 334 1768090 1567983128 0 1567983128 0 "interfaces//VX_dcache_response_inter.v"
S 528 1573270 1567972030 0 1567972030 0 "interfaces//VX_forward_exe_inter.v"
S 610 1573271 1567971856 0 1567971856 0 "interfaces//VX_forward_mem_inter.sv"
S 377 1582724 1567978250 0 1567978250 0 "interfaces//VX_forward_reqeust_inter.v"
@ -35,28 +39,32 @@ S 995 1572568 1567701364 0 1567701364 0 "interfaces
S 654 1573355 1567969270 0 1567969270 0 "interfaces//VX_mw_wb_inter.v"
S 603 1571976 1567568452 0 1567568452 0 "interfaces//VX_warp_ctl_inter.v"
S 450 1572588 1567702406 0 1567702406 0 "interfaces//VX_wb_inter.v"
T 1222614 1701587 1567982098 0 1567982098 0 "obj_dir/VVortex.cpp"
T 44219 1701584 1567982098 0 1567982098 0 "obj_dir/VVortex.h"
T 1791 1701678 1567982098 0 1567982098 0 "obj_dir/VVortex.mk"
T 914 1701674 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 1701673 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1133 1701670 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1208 1701669 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 882 1701666 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 1701665 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 1701668 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 1701667 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 883 1701664 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 1701663 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 1701676 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 1701675 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 821 1701672 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 1701671 1567982098 0 1567982098 0 "obj_dir/VVortex_VX_wb_inter.h"
T 2771 1701575 1567982098 0 1567982098 0 "obj_dir/VVortex__Syms.cpp"
T 1589 1701572 1567982098 0 1567982098 0 "obj_dir/VVortex__Syms.h"
T 1697 1701679 1567982098 0 1567982098 0 "obj_dir/VVortex__ver.d"
T 0 0 1567982098 0 1567982098 0 "obj_dir/VVortex__verFiles.dat"
T 1459 1701677 1567982098 0 1567982098 0 "obj_dir/VVortex_classes.mk"
T 1245424 1768261 1567985240 0 1567985240 0 "obj_dir/VVortex.cpp"
T 44414 1768258 1567985240 0 1567985240 0 "obj_dir/VVortex.h"
T 1791 1768353 1567985240 0 1567985240 0 "obj_dir/VVortex.mk"
T 914 1768341 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_branch_response_inter.cpp"
T 1029 1768340 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_branch_response_inter.h"
T 1210 1768345 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_dcache_request_inter.cpp"
T 1135 1768344 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_dcache_request_inter.h"
T 988 1768343 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_dcache_response_inter.cpp"
T 1045 1768342 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_dcache_response_inter.h"
T 1133 1703195 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
T 1208 1703186 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
T 884 1768351 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
T 1008 1768350 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
T 865 1703171 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
T 987 1703170 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
T 885 1768349 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
T 1005 1768348 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_mem_req_inter.h"
T 902 1768347 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
T 1017 1768346 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
T 821 1768339 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_wb_inter.cpp"
T 954 1768338 1567985240 0 1567985240 0 "obj_dir/VVortex_VX_wb_inter.h"
T 3499 1703157 1567985240 0 1567985240 0 "obj_dir/VVortex__Syms.cpp"
T 1855 1703150 1567985240 0 1567985240 0 "obj_dir/VVortex__Syms.h"
T 2003 1768354 1567985240 0 1567985240 0 "obj_dir/VVortex__ver.d"
T 0 0 1567985240 0 1567985240 0 "obj_dir/VVortex__verFiles.dat"
T 1530 1768352 1567985240 0 1567985240 0 "obj_dir/VVortex_classes.mk"
S 6179 1572602 1567698562 0 1567698562 0 "pipe_regs//VX_d_e_reg.v"
S 1538 1573254 1567973402 0 1567973402 0 "pipe_regs//VX_e_m_reg.v"
S 755 1591921 1567978394 0 1567978394 0 "pipe_regs//VX_f_d_reg.v"

8
rtl/obj_dir/VVortex_classes.mk
View file

@ -18,13 +18,15 @@ VM_TRACE_THREADED = 0
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVortex \
VVortex_VX_mem_req_inter \
VVortex_VX_inst_mem_wb_inter \
VVortex_VX_inst_meta_inter \
VVortex_VX_dcache_response_inter \
VVortex_VX_dcache_request_inter \
VVortex_VX_frE_to_bckE_req_inter \
VVortex_VX_wb_inter \
VVortex_VX_branch_response_inter \
VVortex_VX_warp_ctl_inter \
VVortex_VX_inst_meta_inter \
VVortex_VX_mem_req_inter \
VVortex_VX_inst_mem_wb_inter \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \

BIN
rtl/obj_dir/test_bench.o
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Binary file not shown.

2
rtl/results.txt
View file

@ -3,5 +3,5 @@
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.01056
# time to simulate: 2.19792e-314 milliseconds
# time to simulate: 2.12501e-314 milliseconds
# GRADE: Failed on test: 4294967295