updated documentation for both altera and xilinx FPGA setup

docs/altera_fpga_guide.md

@@ -53,7 +53,7 @@ If the build fails and you need to restart it, clean up the build folder using t
 
     $ make clean
 
-The file `vortex_afu.gbs` should exist when the build is done:
+The bitstream file `vortex_afu.gbs` should exist when the build is done:
 
     $ ls -lsa <build_dir>/synth/vortex_afu.gbs
 
@@ -65,10 +65,15 @@ Signing the bitstream and Programming the FPGA
     $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs
     $ fpgasupdate vortex_afu_unsigned_ssl.gbs
 
-FPGA sample test running OpenCL sgemm kernel
---------------------------------------------
+Sample FPGA Run Test
+--------------------
 
-Run the following from the Vortex root directory
+Ensure you have the correct opae runtime for the FPGA target
+
+    $ make -C runtime/opae clean
+    $ TARGET=FPGA make -C runtime/opae
+
+Run the following from your Vortex build directory
 
     $ TARGET=fpga ./ci/blackbox.sh --driver=opae --app=sgemm --args="-n128"
 

docs/index.md

@@ -7,7 +7,8 @@
 - [Cache Subsystem](cache_subsystem.md)
 - [Software](software.md)
 - [Simulation](simulation.md)
-- [FPGA Setup Guide](fpga_setup.md)
+- [Altera FPGA Setup Guide](altera_fpga_guide.md)
+- [Xilinx FPGA Setup Guide](xilinx_fpga_guide.md)
 - [Debugging](debugging.md)
 - [Useful Links](references.md)
 
@@ -27,6 +28,6 @@ Running Vortex simulators with different configurations:
 
     $ ./ci/blackbox.sh --driver=opae --clusters=1 --cores=4 --warps=4 --threads=2 --app=demo
 
-- Run dogfood driver test with simx driver and Vortex config of 4 cluster, 4 cores, 8 warps, 6 threads 
+- Run dogfood driver test with simx driver and Vortex config of 4 cluster, 4 cores, 8 warps, 6 threads
 
     $ ./ci/blackbox.sh --driver=simx --clusters=4 --cores=4 --warps=8 --threads=6  --app=dogfood

docs/xilinx_fpga_guide.md

@@ -0,0 +1,36 @@
+# FPGA Startup and Configuration Guide
+
+XRT Environment Setup
+----------------------
+
+    $ source /opt/xilinx/Vitis/2023.1/settings64.sh
+    $ source /opt/xilinx/xrt/setup.sh
+
+
+Check Installed FPGA Platforms
+------------------------------
+
+    $ platforminfo -l
+
+
+Build FPGA image
+----------------
+
+    $ cd hw/syn/xilinx/xrt
+    $ PREFIX=test1 PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 TARGET=hw NUM_CORES=4 make
+
+Will run the synthesis under new build directory: BUILD_DIR := "\<PREFIX>\_\<PLATFORM>\_\<TARGET>"
+
+The generated bitstream will be located under <BUILD_DIR>/bin/vortex_afu.xclbin
+
+Sample FPGA Run Test
+--------------------
+
+Ensure you have the correct opae runtime for the FPGA target
+
+    $ make -C runtime/xrt clean
+    $ TARGET=hw make -C runtime/xrt
+
+Run the following from your Vortex build directory
+
+    $ TARGET=hw FPGA_BIN_DIR=<BUILD_DIR>/bin ./ci/blackbox.sh --driver=xrt --app=sgemm --args="-n128"

runtime/xrt/vortex.cpp

@@ -134,12 +134,14 @@ static void wait_for_enter(const std::string &msg) {
 class vx_device {
 public:
   vx_device()
-    : xrtDevice_(nullptr)
-    , xrtKernel_(nullptr)
-    , global_mem_(ALLOC_BASE_ADDR,
+    : global_mem_(ALLOC_BASE_ADDR,
                   GLOBAL_MEM_SIZE - ALLOC_BASE_ADDR,
                   RAM_PAGE_SIZE,
                   CACHE_BLOCK_SIZE)
+  #ifndef CPP_API
+    , xrtDevice_(nullptr)
+    , xrtKernel_(nullptr)
+  #endif
   {}
 
   ~vx_device() {
@@ -715,10 +717,10 @@ public:
 
 private:
 
+  MemoryAllocator global_mem_;
   xrt_device_t xrtDevice_;
   xrt_kernel_t xrtKernel_;
   platform_info_t platform_;
-  MemoryAllocator global_mem_;
   uint64_t dev_caps_;
   uint64_t isa_caps_;
   uint64_t global_mem_size_;