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added rsp map

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This commit is contained in:
trmontgomery 2020-07-19 00:08:09 -04:00
parent 2d39e0561c
commit ed3a0cfa4d
37 changed files with 13615 additions and 60046 deletions
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4
hw/rtl/cache/VX_cache.v vendored
View file

@ -44,7 +44,7 @@ module VX_cache #(
parameter SNOOP_FORWARDING = 0,
// Prefetcher
parameter PRFQ_SIZE = 0,
parameter PRFQ_SIZE = 1,
parameter PRFQ_STRIDE = 0,
// core request tag size
@ -492,4 +492,4 @@ module VX_cache #(
.snp_rsp_ready (snp_rsp_ready)
);
endmodule
endmodule

4
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View file

@ -10,7 +10,7 @@ module VX_cache_dram_req_arb #(
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 0,
// Prefetcher
parameter PRFQ_SIZE = 0,
parameter PRFQ_SIZE = 1,
parameter PRFQ_STRIDE = 0
) (
input wire clk,
@ -117,4 +117,4 @@ module VX_cache_dram_req_arb #(
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
endmodule
endmodule

4
hw/rtl/cache/VX_prefetcher.v vendored
View file

@ -5,7 +5,7 @@ module VX_prefetcher #(
parameter BANK_LINE_SIZE = 0,
// Size of a word in bytes
parameter WORD_SIZE = 0,
parameter PRFQ_SIZE = 0,
parameter PRFQ_SIZE = 1,
parameter PRFQ_STRIDE = 0
) (
input wire clk,
@ -68,4 +68,4 @@ module VX_prefetcher #(
end
end
endmodule
endmodule

6
hw/rtl/libs/VX_generic_queue.v
View file

@ -1,8 +1,8 @@
`include "VX_define.vh"
module VX_generic_queue #(
parameter DATAW = 1,
parameter SIZE = 16,
parameter DATAW = 0,
parameter SIZE = 1,
parameter BUFFERED_OUTPUT = 1
) (
input wire clk,
@ -164,4 +164,4 @@ module VX_generic_queue #(
end
end
endmodule
endmodule

94
hw/unit_tests/cache/cachesim.cpp vendored
View file

@ -3,6 +3,7 @@
#include <iomanip>
#include <iostream>
#include <vector>
#include <map>
uint64_t timestamp = 0;
@ -33,6 +34,7 @@ CacheSim::~CacheSim() {
trace_->close();
//#endif
delete cache_;
//need to delete the req and rsp vectors
}
void CacheSim::attach_ram(RAM* ram) {
@ -74,24 +76,33 @@ void CacheSim::eval() {
}
void CacheSim::run(){
#ifndef NDEBUG
//#ifndef NDEBUG
std::cout << timestamp << ": [sim] run()" << std::endl;
#endif
// reset the device
this->reset();
this->step();
//#endif
this->step();
int valid = 15;
// execute program
while (!core_req_vec_.empty()) {
for(int i = 0; i < 10; ++i){
if(i == 1){
this->clear_req(); //invalidate reqs
}
this->step();
}
}
/*
while(valid > 10){
this->step();
if(!cache_->core_req_valid && !cache_->core_rsp_valid){
valid--;
}
}
*/
}
void CacheSim::clear_req(){
@ -101,6 +112,8 @@ void CacheSim::clear_req(){
void CacheSim::send_req(core_req_t *req){
core_req_vec_.push(req);
unsigned int *data = new unsigned int[4];
core_rsp_vec_.insert(std::pair<unsigned int, unsigned int*>(req->tag, data));
}
bool CacheSim::get_core_req_ready(){
@ -111,49 +124,11 @@ bool CacheSim::get_core_rsp_ready(){
return cache_->core_rsp_ready;
}
void CacheSim::set_core_req(){
cache_->core_req_valid = 0xf;
cache_->core_req_rw = 0xf;
cache_->core_req_byteen = 0xffff;
cache_->core_req_addr[0] = 0x00;
cache_->core_req_addr[1] = 0xab;
cache_->core_req_addr[2] = 0xcd;
cache_->core_req_addr[3] = 0xe1;
cache_->core_req_data[0] = 0xffffffff;
cache_->core_req_data[1] = 0x11111111;
cache_->core_req_data[2] = 0x22222222;
cache_->core_req_data[3] = 0x33333333;
cache_->core_req_tag = 0xff;
}
void CacheSim::set_core_req2(){
cache_->core_req_valid = 0xf; //b1000
cache_->core_req_rw = 0x0; //b0000
cache_->core_req_byteen = 0xffff;
cache_->core_req_addr[0] = 0x00;
cache_->core_req_addr[1] = 0xab;
cache_->core_req_addr[2] = 0xcd;
cache_->core_req_addr[3] = 0xe1;
cache_->core_req_data[0] = 0x1111111;
cache_->core_req_data[1] = 0x4444444;
cache_->core_req_data[2] = 0x5555555;
cache_->core_req_data[3] = 0x6666666;
cache_->core_req_tag = 0xff;
}
void CacheSim::eval_reqs(){
//check to see if cache is accepting reqs
if(!core_req_vec_.empty() && cache_->core_req_ready){
core_req_t *req = core_req_vec_.front();
std::cout << "Display Req Data Contents " << std::endl;
std::cout << std::hex << "Data[0]: " << req->data[0] << std::endl;
std::cout << std::hex << "Data[1]: " << req->data[1] << std::endl;
std::cout << std::hex << "Data[2]: " << req->data[2] << std::endl;
std::cout << std::hex << "Data[3]: " << req->data[3] << std::endl;
cache_->core_req_valid = req->valid;
cache_->core_req_rw = req->rw;
cache_->core_req_byteen = req->byteen;
@ -170,19 +145,22 @@ void CacheSim::eval_reqs(){
cache_->core_req_tag = req->tag;
std::cout << "Display Cache Data inputs: " << std::endl;
get_core_req();
core_req_vec_.pop();
std::cout << "Req Popped" << std::endl;
} else {
clear_req();
}
}
void CacheSim::eval_rsps(){
//check to see if a request has been responded to
//if core_rsp tag equal to the front queue tag pop it from the queue
//while the req tag == rsp tag
if (cache_->core_rsp_valid){
core_rsp_vec_.at(cache_->core_rsp_tag)[0] = cache_->core_rsp_data[0];
core_rsp_vec_.at(cache_->core_rsp_tag)[1] = cache_->core_rsp_data[1];
core_rsp_vec_.at(cache_->core_rsp_tag)[2] = cache_->core_rsp_data[2];
core_rsp_vec_.at(cache_->core_rsp_tag)[3] = cache_->core_rsp_data[3];
}
}
void CacheSim::eval_dram_bus() {
@ -264,10 +242,14 @@ void CacheSim::eval_dram_bus() {
//DEBUG
void CacheSim::get_core_rsp(){
std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
void CacheSim::get_core_rsp(unsigned int (&rsp)[4]){
rsp[0] = cache_->core_rsp_data[0];
rsp[1] = cache_->core_rsp_data[1];
rsp[2] = cache_->core_rsp_data[2];
rsp[3] = cache_->core_rsp_data[3];
//std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
//std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
//std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
}
void CacheSim::get_core_req(){

3
hw/unit_tests/cache/cachesim.h vendored
View file

@ -58,7 +58,7 @@ public:
//display funcs
void get_dram_req();
void get_core_rsp();
void get_core_rsp(unsigned int (&rsp)[4]);
void get_core_req();
bool get_core_req_ready();
bool get_core_rsp_ready();
@ -75,6 +75,7 @@ private:
std::queue<core_req_t*> core_req_vec_;
std::vector<dram_req_t> dram_rsp_vec_;
std::map<unsigned int, unsigned int*> core_rsp_vec_;
int dram_rsp_active_;
uint32_t snp_req_active_;

BIN
hw/unit_tests/cache/obj_dir/VVX_cache vendored
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28288
hw/unit_tests/cache/obj_dir/VVX_cache.cpp vendored
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File diff suppressed because it is too large Load diff

955
hw/unit_tests/cache/obj_dir/VVX_cache.h vendored
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@ -1,955 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_CACHE_H_
#define _VVX_CACHE_H_ // guard
#include "verilated_heavy.h"
//==========
class VVX_cache__Syms;
class VVX_cache_VerilatedVcd;
//----------
VL_MODULE(VVX_cache) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(core_req_valid,3,0);
VL_IN8(core_req_rw,3,0);
VL_IN16(core_req_byteen,15,0);
VL_OUT8(core_req_ready,0,0);
VL_OUT8(core_rsp_valid,3,0);
VL_IN8(core_rsp_ready,0,0);
VL_OUT8(dram_req_valid,0,0);
VL_OUT8(dram_req_rw,0,0);
VL_IN8(dram_req_ready,0,0);
VL_IN8(dram_rsp_valid,0,0);
VL_OUT8(dram_rsp_ready,0,0);
VL_IN8(snp_req_valid,0,0);
VL_IN8(snp_req_invalidate,0,0);
VL_OUT8(snp_req_ready,0,0);
VL_OUT8(snp_rsp_valid,0,0);
VL_IN8(snp_rsp_ready,0,0);
VL_OUT8(snp_fwdout_valid,1,0);
VL_OUT8(snp_fwdout_invalidate,1,0);
VL_OUT8(snp_fwdout_tag,1,0);
VL_IN8(snp_fwdout_ready,1,0);
VL_IN8(snp_fwdin_valid,1,0);
VL_IN8(snp_fwdin_tag,1,0);
VL_OUT8(snp_fwdin_ready,1,0);
VL_OUT16(dram_req_byteen,15,0);
VL_INW(core_req_addr,119,0,4);
VL_INW(core_req_data,127,0,4);
VL_OUTW(core_rsp_data,127,0,4);
VL_OUT(dram_req_addr,27,0);
VL_OUTW(dram_req_data,127,0,4);
VL_OUT(dram_req_tag,27,0);
VL_INW(dram_rsp_data,127,0,4);
VL_IN(dram_rsp_tag,27,0);
VL_IN(snp_req_addr,27,0);
VL_IN(snp_req_tag,27,0);
VL_OUT(snp_rsp_tag,27,0);
VL_OUT64(snp_fwdout_addr,55,0);
VL_IN64(core_req_tag,41,0);
VL_OUT64(core_rsp_tag,41,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Anonymous structures to workaround compiler member-count bugs
struct {
CData/*3:0*/ VX_cache__DOT__per_bank_core_req_ready;
CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_valid;
CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_tid;
CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_ready;
CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid;
CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready;
CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready;
CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid;
CData/*3:0*/ VX_cache__DOT__per_bank_snp_req_ready;
CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_valid;
CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_ready;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid;
CData/*3:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request;
CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r;
CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual;
CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value;
CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original;
CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
CData/*1:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank;
CData/*0:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid;
CData/*3:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
};
struct {
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr;
CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr;
CData/*4:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r;
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r;
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r;
QData/*63:0*/ VX_cache__DOT__per_bank_dram_wb_req_byteen;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready;
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match;
WData/*127:0*/ VX_cache__DOT__per_bank_core_rsp_data[4];
WData/*111:0*/ VX_cache__DOT__per_bank_dram_fill_req_addr[4];
WData/*111:0*/ VX_cache__DOT__per_bank_dram_wb_req_addr[4];
WData/*511:0*/ VX_cache__DOT__per_bank_dram_wb_req_data[16];
WData/*111:0*/ VX_cache__DOT__per_bank_snp_rsp_tag[4];
IData/*27:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr;
IData/*27:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r;
WData/*111:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4];
WData/*111:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4];
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4];
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4];
IData/*31:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
IData/*31:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i;
IData/*31:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
IData/*31:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i;
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0;
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0;
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5];
};
struct {
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
WData/*119:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[4];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[4];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[10];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i;
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[8];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[4];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i;
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j;
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[6];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[10];
WData/*415:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[13];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7];
IData/*29:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0;
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WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5];
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QData/*63:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
};
struct {
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QData/*63:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
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QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r;
QData/*41:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag;
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty;
QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid;
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[1];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[1];
CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[1];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[1];
QData/*48:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
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IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
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WData/*84:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[1];
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CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[1];
IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[1];
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WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
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WData/*84:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
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WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[1];
};
struct {
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[1];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[1];
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CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[1];
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1];
CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1];
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1];
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4];
WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4];
IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64];
SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64];
WData/*84:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7];
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Anonymous structures to workaround compiler member-count bugs
struct {
SData/*15:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid;
CData/*3:0*/ __Vtableidx1;
CData/*3:0*/ __Vtableidx2;
CData/*3:0*/ __Vtableidx3;
CData/*3:0*/ __Vtableidx4;
CData/*3:0*/ __Vtableidx5;
CData/*3:0*/ __Vtableidx6;
CData/*3:0*/ __Vtableidx7;
CData/*3:0*/ __Vtableidx8;
CData/*0:0*/ __Vclklast__TOP__clk;
WData/*127:0*/ VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[4];
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4];
WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5];
WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5];
WData/*242:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8];
WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3];
WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7];
WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10];
WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10];
WData/*165:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6];
IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1;
IData/*31:0*/ __Vm_traceActivity;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
};
struct {
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out;
QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in;
};
static CData/*1:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16];
static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16];
static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16];
static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16];
static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16];
static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16];
static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16];
static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16];
static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
static CData/*0:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
static IData/*31:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
static CData/*0:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
static IData/*31:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
static CData/*0:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
static IData/*31:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
static CData/*1:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16];
static CData/*0:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16];
static IData/*31:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16];
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_cache__Syms* __VlSymsp; // Symbol table
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_cache); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_cache(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_cache();
/// Trace signals in the model; called by application code
void trace(VerilatedVcdC* tfp, int levels, int options = 0);
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step.
void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes.
void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_cache__Syms* symsp, bool first);
private:
static QData _change_request(VVX_cache__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp);
static void _combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(VVX_cache__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp);
static void _settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD;
static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
//----------
#endif // guard

70
hw/unit_tests/cache/obj_dir/VVX_cache.mk vendored
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@ -1,70 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_cache.mk
default: VVX_cache
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_cache
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_cache
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
cachesim \
testbench \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include VVX_cache_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
cachesim.o: cachesim.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
testbench.o: testbench.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
VVX_cache: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
# Verilated -*- Makefile -*-

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hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a vendored
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hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp vendored
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@ -1,3 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVX_cache.cpp"

4
hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d vendored
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@ -1,4 +0,0 @@
VVX_cache__ALLcls.o: VVX_cache__ALLcls.cpp VVX_cache.cpp VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h

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hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o vendored
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hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp vendored
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@ -1,5 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "VVX_cache__Trace.cpp"
#include "VVX_cache__Syms.cpp"
#include "VVX_cache__Trace__Slow.cpp"

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hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d vendored
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VVX_cache__ALLsup.o: VVX_cache__ALLsup.cpp VVX_cache__Trace.cpp \
/usr/local/share/verilator/include/verilated_vcd_c.h \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h VVX_cache__Syms.h \
/usr/local/share/verilator/include/verilated_heavy.h VVX_cache.h \
VVX_cache__Syms.cpp VVX_cache__Trace__Slow.cpp

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hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o vendored
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hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp vendored
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_cache__Syms.h"
#include "VVX_cache.h"
// FUNCTIONS
VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
// Setup scopes
__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER);
__Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _VVX_CACHE__SYMS_H_
#define _VVX_CACHE__SYMS_H_ // guard
#include "verilated_heavy.h"
// INCLUDE MODULE CLASSES
#include "VVX_cache.h"
// SYMS CLASS
class VVX_cache__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
// SUBCELL STATE
VVX_cache* TOPp;
// SCOPE NAMES
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue;
VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue;
VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2;
// CREATORS
VVX_cache__Syms(VVX_cache* topp, const char* namep);
~VVX_cache__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard

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hw/unit_tests/cache/obj_dir/VVX_cache__ver.d vendored
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@ -1 +0,0 @@
obj_dir/VVX_cache.cpp obj_dir/VVX_cache.h obj_dir/VVX_cache.mk obj_dir/VVX_cache__Syms.cpp obj_dir/VVX_cache__Syms.h obj_dir/VVX_cache__Trace.cpp obj_dir/VVX_cache__Trace__Slow.cpp obj_dir/VVX_cache__ver.d obj_dir/VVX_cache_classes.mk : /usr/local/bin/verilator_bin ../../rtl//VX_config.vh ../../rtl//VX_define.vh ../../rtl//VX_scope.vh ../../rtl//VX_user_config.vh ../../rtl/cache/VX_bank.v ../../rtl/cache/VX_bank_core_req_arb.v ../../rtl/cache/VX_cache.v ../../rtl/cache/VX_cache_config.vh ../../rtl/cache/VX_cache_core_req_bank_sel.v ../../rtl/cache/VX_cache_core_rsp_merge.v ../../rtl/cache/VX_cache_dram_fill_arb.v ../../rtl/cache/VX_cache_dram_req_arb.v ../../rtl/cache/VX_cache_miss_resrv.v ../../rtl/cache/VX_prefetcher.v ../../rtl/cache/VX_snp_forwarder.v ../../rtl/cache/VX_snp_rsp_arb.v ../../rtl/cache/VX_tag_data_access.v ../../rtl/cache/VX_tag_data_structure.v ../../rtl/libs/VX_fair_arbiter.v ../../rtl/libs/VX_fixed_arbiter.v ../../rtl/libs/VX_generic_queue.v ../../rtl/libs/VX_generic_register.v ../../rtl/libs/VX_indexable_queue.v ../../rtl/libs/VX_priority_encoder.v /usr/local/bin/verilator_bin

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# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp"
S 7349 4983714 1594698569 774801969 1594698569 774801969 "../../rtl//VX_config.vh"
S 9046 4983721 1594698569 778802144 1594698569 778802144 "../../rtl//VX_define.vh"
S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh"
S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh"
S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v"
S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank_core_req_arb.v"
S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v"
S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh"
S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v"
S 3649 4983746 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_core_rsp_merge.v"
S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v"
S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v"
S 7304 4983749 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_miss_resrv.v"
S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v"
S 5067 4983751 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_snp_forwarder.v"
S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v"
S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v"
S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v"
S 1861 4983777 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fair_arbiter.v"
S 1022 4983778 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fixed_arbiter.v"
S 5977 4983779 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_queue.v"
S 586 4983780 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_register.v"
S 1560 4983782 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_indexable_queue.v"
S 495 4983785 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_priority_encoder.v"
S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin"
T 2996411 4983824 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.cpp"
T 93498 4983825 1594698591 211740363 1594698591 211740363 "obj_dir/VVX_cache.h"
T 2104 4983826 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.mk"
T 8694 4983827 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.cpp"
T 4866 4983828 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.h"
T 429475 4983829 1594698591 207740187 1594698591 207740187 "obj_dir/VVX_cache__Trace.cpp"
T 700909 4983830 1594698591 195739663 1594698591 195739663 "obj_dir/VVX_cache__Trace__Slow.cpp"
T 1118 4980960 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__ver.d"
T 0 0 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__verFiles.dat"
T 1315 4983831 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache_classes.mk"

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@ -1,43 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_cache.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
# Tracing threaded output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_cache \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
VVX_cache__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_cache__Syms \
VVX_cache__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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@ -1,6 +0,0 @@
cache_sim.o: ../cache_sim.cpp VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h

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@ -1,6 +0,0 @@
cachesim.o: ../cachesim.cpp ../cachesim.h VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

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hw/unit_tests/cache/obj_dir/testbench.d vendored
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@ -1,6 +0,0 @@
testbench.o: ../testbench.cpp ../cachesim.h VVX_cache.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \
VVX_cache.h /usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h ../ram.h

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8
hw/unit_tests/cache/obj_dir/verilated.d vendored
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@ -1,8 +0,0 @@
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated_imp.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_heavy.h \
/usr/local/share/verilator/include/verilated_syms.h \
/usr/local/share/verilator/include/verilated_sym_props.h \
/usr/local/share/verilator/include/verilated_config.h

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4
hw/unit_tests/cache/obj_dir/verilated_vcd_c.d vendored
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@ -1,4 +0,0 @@
verilated_vcd_c.o: /usr/local/share/verilator/include/verilated_vcd_c.cpp \
/usr/local/share/verilator/include/verilatedos.h \
/usr/local/share/verilator/include/verilated.h \
/usr/local/share/verilator/include/verilated_vcd_c.h

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40
hw/unit_tests/cache/testbench.cpp vendored
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@ -5,15 +5,31 @@
#define VCD_OUTPUT 1
void check_match(unsigned int *data, unsigned int *rsp, char &check){
for(int i =0; i < 4; ++i){
for(int j = 0; j < 4; ++j){
std::cout << data[i] << std::endl;
std::cout << rsp[j] << std::endl;
if (data[i] == rsp[j]){
check = check | i;
std::cout << std::hex << check << std::endl;
}
}
}
}
int main(int argc, char **argv)
{
//init
RAM ram;
CacheSim cachesim;
cachesim.attach_ram(&ram);
cachesim.reset();
unsigned int addr[4] = {0x12222222, 0xabbbbbbb, 0xcddddddd, 0xe4444444};
unsigned int data[4] = {0xffffffff, 0x11111111, 0x22222222, 0x33333333};
unsigned int rsp[4] = {0,0,0,0};
char responded = 0;
//write req
core_req_t* write = new core_req_t;
write->valid = 0xf;
@ -31,35 +47,15 @@ int main(int argc, char **argv)
read->addr = addr;
read->data = addr;
read->tag = 0xff;
// reset the device
cachesim.reset();
//queue reqs
cachesim.send_req(write);
cachesim.send_req(read);
cachesim.step();
//cachesim.get_core_req();
//write block to cache
// cachesim.set_core_req();
for (int i = 0; i < 100; ++i){
/*if(i == 1){
cachesim.clear_req();
}*/
cachesim.run();
for(int i = 0; i < 100; ++i){
cachesim.step();
}
cachesim.get_core_req();
// read block
//cachesim.set_core_req2();
for (int i = 0; i < 100; ++i){
if(i == 1){
//read block from cache
cachesim.clear_req();
}
cachesim.step();
}
return 0;
}

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