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arbitration update

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This commit is contained in:
Blaise Tine 2024-08-12 04:09:56 -07:00
parent 6f3add273d
commit ed66ee2806
13 changed files with 116 additions and 175 deletions
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6
hw/rtl/cache/VX_cache.sv vendored
View file

@ -317,7 +317,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.NUM_OUTPUTS (NUM_BANKS),
.DATAW (CORE_REQ_DATAW),
.PERF_CTR_BITS (`PERF_CTR_BITS),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (REQ_XBAR_BUF)
) req_xbar (
.clk (clk),
@ -452,7 +452,7 @@ module VX_cache import VX_gpu_pkg::*; #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
.DATAW (CORE_RSP_DATAW),
.ARBITER ("F")
.ARBITER ("R")
) rsp_xbar (
.clk (clk),
.reset (rsp_xbar_reset),
@ -501,7 +501,7 @@ module VX_cache import VX_gpu_pkg::*; #(
VX_stream_arb #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (`CS_MEM_ADDR_WIDTH + 1 + LINE_SIZE + `CS_LINE_WIDTH + MSHR_ADDR_WIDTH + 1),
.ARBITER ("F")
.ARBITER ("R")
) mem_req_arb (
.clk (clk),
.reset (reset),

2
hw/rtl/core/VX_alu_muldiv.sv
View file

@ -324,7 +324,7 @@ module VX_alu_muldiv #(
VX_stream_arb #(
.NUM_INPUTS (2),
.DATAW (TAG_WIDTH + (NUM_LANES * `XLEN)),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (1)
) rsp_buf (
.clk (clk),

2
hw/rtl/core/VX_alu_unit.sv
View file

@ -121,7 +121,7 @@ module VX_alu_unit #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
.OUT_BUF (PARTIAL_BW ? 1 : 3),
.ARBITER ("F")
.ARBITER ("R")
) rsp_arb (
.clk (clk),
.reset (block_reset),

2
hw/rtl/core/VX_operands.sv
View file

@ -23,7 +23,7 @@
module VX_operands import VX_gpu_pkg::*; #(
parameter `STRING INSTANCE_ID = "",
parameter NUM_BANKS = 4,
parameter OUT_BUF = 8+4 // using 2-cycle LUT EB for area reduction
parameter OUT_BUF = 3
) (
input wire clk,
input wire reset,

4
hw/rtl/core/VX_scoreboard.sv
View file

@ -289,8 +289,8 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
VX_stream_arb #(
.NUM_INPUTS (PER_ISSUE_WARPS),
.DATAW (DATAW),
.ARBITER ("F"),
.OUT_BUF (8+4) // using 2-cycle LUT EB for area reduction
.ARBITER ("R"),
.OUT_BUF (3)
) out_arb (
.clk (clk),
.reset (arb_reset),

2
hw/rtl/fpu/VX_fpu_dpi.sv
View file

@ -470,7 +470,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
VX_stream_arb #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_DATAW),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (OUT_BUF)
) rsp_arb (
.clk (clk),

2
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -296,7 +296,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
VX_stream_arb #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_DATAW + 2),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (OUT_BUF)
) rsp_arb (
.clk (clk),

2
hw/rtl/libs/VX_avs_adapter.sv
View file

@ -199,7 +199,7 @@ module VX_avs_adapter #(
VX_stream_arb #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (DATA_WIDTH + TAG_WIDTH),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (RSP_OUT_BUF)
) rsp_arb (
.clk (clk),

4
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -203,11 +203,11 @@ module VX_axi_adapter #(
`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rlast[i] == 1, ("%t: *** AXI response error", $time));
`RUNTIME_ASSERT(~m_axi_rvalid[i] || m_axi_rresp[i] == 0, ("%t: *** AXI response error", $time));
end
VX_stream_arb #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (DATA_WIDTH + TAG_WIDTH),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (RSP_OUT_BUF)
) rsp_arb (
.clk (clk),

66
hw/rtl/libs/VX_fair_arbiter.sv
View file

@ -1,66 +0,0 @@
// Copyright © 2019-2023
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`include "VX_platform.vh"
`TRACING_OFF
module VX_fair_arbiter #(
parameter NUM_REQS = 1,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid,
input wire grant_ready
);
if (NUM_REQS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (grant_ready)
assign grant_index = '0;
assign grant_onehot = requests;
assign grant_valid = requests[0];
end else begin
reg [NUM_REQS-1:0] reqs_mask;
wire [NUM_REQS-1:0] masked_reqs = requests & reqs_mask;
wire [NUM_REQS-1:0] requests_qual = (| masked_reqs) ? masked_reqs : requests;
always @(posedge clk) begin
if (reset) begin
reqs_mask <= '1;
end else if (grant_valid && grant_ready) begin
reqs_mask <= (| reqs_mask) ? (reqs_mask & ~grant_onehot) : ~grant_onehot;
end
end
VX_priority_encoder #(
.N (NUM_REQS)
) priority_enc (
.data_in (requests_qual),
.index_out (grant_index),
.onehot_out (grant_onehot),
.valid_out (grant_valid)
);
end
endmodule
`TRACING_ON

14
hw/rtl/libs/VX_generic_arbiter.sv
View file

@ -56,20 +56,6 @@ module VX_generic_arbiter #(
.grant_ready (grant_ready)
);
end else if (TYPE == "F") begin
VX_fair_arbiter #(
.NUM_REQS (NUM_REQS)
) fair_arbiter (
.clk (clk),
.reset (reset),
.requests (requests),
.grant_valid (grant_valid),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_ready (grant_ready)
);
end else if (TYPE == "M") begin
VX_matrix_arbiter #(

183
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -16,7 +16,7 @@
`TRACING_OFF
module VX_rr_arbiter #(
parameter NUM_REQS = 1,
parameter MODEL = 1,
parameter MODEL = 2,
parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS),
parameter LUT_OPT = 0
) (
@ -41,14 +41,15 @@ module VX_rr_arbiter #(
end else if (LUT_OPT && NUM_REQS == 2) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
3'b0_01,
3'b1_?1: begin grant_onehot_r = 2'b01; grant_index_r = LOG_NUM_REQS'(0); end
default: begin grant_onehot_r = 2'b10; grant_index_r = LOG_NUM_REQS'(1); end
3'b1_?1: begin grant_index_r = LOG_NUM_REQS'(0); end
3'b0_1?,
3'b1_10: begin grant_index_r = LOG_NUM_REQS'(1); end
default: begin grant_index_r = 'x; end
endcase
end
@ -61,24 +62,26 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 3) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
5'b00_001,
5'b01_0?1,
5'b10_??1: begin grant_onehot_r = 3'b001; grant_index_r = LOG_NUM_REQS'(0); end
5'b10_??1: begin grant_index_r = LOG_NUM_REQS'(0); end
5'b00_?1?,
5'b01_010,
5'b10_?10: begin grant_onehot_r = 3'b010; grant_index_r = LOG_NUM_REQS'(1); end
default: begin grant_onehot_r = 3'b100; grant_index_r = LOG_NUM_REQS'(2); end
5'b10_?10: begin grant_index_r = LOG_NUM_REQS'(1); end
5'b00_10?,
5'b01_1??,
5'b10_100: begin grant_index_r = LOG_NUM_REQS'(2); end
default: begin grant_index_r = 'x; end
endcase
end
@ -91,13 +94,12 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 4) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
@ -105,16 +107,20 @@ module VX_rr_arbiter #(
6'b00_0001,
6'b01_00?1,
6'b10_0??1,
6'b11_???1: begin grant_onehot_r = 4'b0001; grant_index_r = LOG_NUM_REQS'(0); end
6'b11_???1: begin grant_index_r = LOG_NUM_REQS'(0); end
6'b00_??1?,
6'b01_0010,
6'b10_0?10,
6'b11_??10: begin grant_onehot_r = 4'b0010; grant_index_r = LOG_NUM_REQS'(1); end
6'b11_??10: begin grant_index_r = LOG_NUM_REQS'(1); end
6'b00_?10?,
6'b01_?1??,
6'b10_0100,
6'b11_?100: begin grant_onehot_r = 4'b0100; grant_index_r = LOG_NUM_REQS'(2); end
default: begin grant_onehot_r = 4'b1000; grant_index_r = LOG_NUM_REQS'(3); end
6'b11_?100: begin grant_index_r = LOG_NUM_REQS'(2); end
6'b00_100?,
6'b01_10??,
6'b10_1???,
6'b11_1000: begin grant_index_r = LOG_NUM_REQS'(3); end
default: begin grant_index_r = 'x; end
endcase
end
@ -127,13 +133,12 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 5) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
@ -142,23 +147,28 @@ module VX_rr_arbiter #(
8'b001_000?1,
8'b010_00??1,
8'b011_0???1,
8'b100_????1: begin grant_onehot_r = 5'b00001; grant_index_r = LOG_NUM_REQS'(0); end
8'b100_????1: begin grant_index_r = LOG_NUM_REQS'(0); end
8'b000_???1?,
8'b001_00010,
8'b010_00?10,
8'b011_0??10,
8'b100_???10: begin grant_onehot_r = 5'b00010; grant_index_r = LOG_NUM_REQS'(1); end
8'b100_???10: begin grant_index_r = LOG_NUM_REQS'(1); end
8'b000_??10?,
8'b001_??1??,
8'b010_00100,
8'b011_0?100,
8'b100_??100: begin grant_onehot_r = 5'b00100; grant_index_r = LOG_NUM_REQS'(2); end
8'b100_??100: begin grant_index_r = LOG_NUM_REQS'(2); end
8'b000_?100?,
8'b001_?10??,
8'b010_?1???,
8'b011_01000,
8'b100_?1000: begin grant_onehot_r = 5'b01000; grant_index_r = LOG_NUM_REQS'(3); end
default: begin grant_onehot_r = 5'b10000; grant_index_r = LOG_NUM_REQS'(4); end
8'b100_?1000: begin grant_index_r = LOG_NUM_REQS'(3); end
8'b000_1000?,
8'b001_100??,
8'b010_10???,
8'b011_1????,
8'b100_10000: begin grant_index_r = LOG_NUM_REQS'(4); end
default: begin grant_index_r = 'x; end
endcase
end
@ -171,13 +181,12 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 6) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
@ -187,32 +196,38 @@ module VX_rr_arbiter #(
9'b010_000??1,
9'b011_00???1,
9'b100_0????1,
9'b101_?????1: begin grant_onehot_r = 6'b000001; grant_index_r = LOG_NUM_REQS'(0); end
9'b101_?????1: begin grant_index_r = LOG_NUM_REQS'(0); end
9'b000_????1?,
9'b001_000010,
9'b010_000?10,
9'b011_00??10,
9'b100_0???10,
9'b101_????10: begin grant_onehot_r = 6'b000010; grant_index_r = LOG_NUM_REQS'(1); end
9'b101_????10: begin grant_index_r = LOG_NUM_REQS'(1); end
9'b000_???10?,
9'b001_???1??,
9'b010_000100,
9'b011_00?100,
9'b100_0??100,
9'b101_???100: begin grant_onehot_r = 6'b000100; grant_index_r = LOG_NUM_REQS'(2); end
9'b101_???100: begin grant_index_r = LOG_NUM_REQS'(2); end
9'b000_??100?,
9'b001_??10??,
9'b010_??1???,
9'b011_001000,
9'b100_0?1000,
9'b101_??1000: begin grant_onehot_r = 6'b001000; grant_index_r = LOG_NUM_REQS'(3); end
9'b101_??1000: begin grant_index_r = LOG_NUM_REQS'(3); end
9'b000_?1000?,
9'b001_?100??,
9'b010_?10???,
9'b011_?1????,
9'b100_010000,
9'b101_?10000: begin grant_onehot_r = 6'b010000; grant_index_r = LOG_NUM_REQS'(4); end
default: begin grant_onehot_r = 6'b100000; grant_index_r = LOG_NUM_REQS'(5); end
9'b101_?10000: begin grant_index_r = LOG_NUM_REQS'(4); end
9'b000_10000?,
9'b001_1000??,
9'b010_100???,
9'b011_10????,
9'b100_1?????,
9'b101_100000: begin grant_index_r = LOG_NUM_REQS'(5); end
default: begin grant_index_r = 'x; end
endcase
end
@ -225,60 +240,66 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 7) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
10'b000_000001,
10'b001_0000?1,
10'b010_000??1,
10'b011_00???1,
10'b100_00???1,
10'b101_0????1,
10'b110_?????1: begin grant_onehot_r = 7'b0000001; grant_index_r = LOG_NUM_REQS'(0); end
10'b000_0000001,
10'b001_00000?1,
10'b010_0000??1,
10'b011_000???1,
10'b100_000???1,
10'b101_00????1,
10'b110_??????1: begin grant_index_r = LOG_NUM_REQS'(0); end
10'b000_?????1?,
10'b001_0000010,
10'b010_0000?10,
10'b011_000??10,
10'b100_00???10,
10'b101_0????10,
10'b110_?????10: begin grant_onehot_r = 7'b0000010; grant_index_r = LOG_NUM_REQS'(1); end
10'b110_?????10: begin grant_index_r = LOG_NUM_REQS'(1); end
10'b000_????10?,
10'b001_????1??,
10'b010_0000100,
10'b011_000?100,
10'b100_00??100,
10'b101_0???100,
10'b110_????100: begin grant_onehot_r = 7'b0000100; grant_index_r = LOG_NUM_REQS'(2); end
10'b110_????100: begin grant_index_r = LOG_NUM_REQS'(2); end
10'b000_???100?,
10'b001_???10??,
10'b010_???1???,
10'b011_0001000,
10'b100_00?1000,
10'b101_0??1000,
10'b110_???1000: begin grant_onehot_r = 7'b0001000; grant_index_r = LOG_NUM_REQS'(3); end
10'b110_???1000: begin grant_index_r = LOG_NUM_REQS'(3); end
10'b000_??1000?,
10'b001_??100??,
10'b010_??10???,
10'b011_??1????,
10'b100_0010000,
10'b101_0?10000,
10'b110_??10000: begin grant_onehot_r = 7'b0010000; grant_index_r = LOG_NUM_REQS'(4); end
10'b110_??10000: begin grant_index_r = LOG_NUM_REQS'(4); end
10'b000_?10000?,
10'b001_?1000??,
10'b010_?100???,
10'b011_?10????,
10'b100_?1?????,
10'b101_0100000,
10'b110_?100000: begin grant_onehot_r = 7'b0100000; grant_index_r = LOG_NUM_REQS'(5); end
default: begin grant_onehot_r = 7'b1000000; grant_index_r = LOG_NUM_REQS'(6); end
10'b110_?100000: begin grant_index_r = LOG_NUM_REQS'(5); end
10'b000_100000?,
10'b001_10000??,
10'b010_1000???,
10'b011_100????,
10'b100_10?????,
10'b101_1??????,
10'b110_1000000: begin grant_index_r = LOG_NUM_REQS'(6); end
default: begin grant_index_r = 'x; end
endcase
end
@ -291,13 +312,12 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 8) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
@ -309,7 +329,7 @@ module VX_rr_arbiter #(
11'b100_000????1,
11'b101_00?????1,
11'b110_0??????1,
11'b111_???????1: begin grant_onehot_r = 8'b00000001; grant_index_r = LOG_NUM_REQS'(0); end
11'b111_???????1: begin grant_index_r = LOG_NUM_REQS'(0); end
11'b000_??????1?,
11'b001_00000010,
11'b010_00000?10,
@ -317,7 +337,7 @@ module VX_rr_arbiter #(
11'b100_000???10,
11'b101_00????10,
11'b110_0?????10,
11'b111_??????10: begin grant_onehot_r = 8'b00000010; grant_index_r = LOG_NUM_REQS'(1); end
11'b111_??????10: begin grant_index_r = LOG_NUM_REQS'(1); end
11'b000_?????10?,
11'b001_?????1??,
11'b010_00000100,
@ -325,7 +345,7 @@ module VX_rr_arbiter #(
11'b100_000??100,
11'b101_00???100,
11'b110_0????100,
11'b111_?????100: begin grant_onehot_r = 8'b00000100; grant_index_r = LOG_NUM_REQS'(2); end
11'b111_?????100: begin grant_index_r = LOG_NUM_REQS'(2); end
11'b000_????100?,
11'b001_????10??,
11'b010_????1???,
@ -333,7 +353,7 @@ module VX_rr_arbiter #(
11'b100_000?1000,
11'b101_00??1000,
11'b110_0???1000,
11'b111_????1000: begin grant_onehot_r = 8'b00001000; grant_index_r = LOG_NUM_REQS'(3); end
11'b111_????1000: begin grant_index_r = LOG_NUM_REQS'(3); end
11'b000_???1000?,
11'b001_???100??,
11'b010_???10???,
@ -341,7 +361,7 @@ module VX_rr_arbiter #(
11'b100_00010000,
11'b101_00?10000,
11'b110_0??10000,
11'b111_???10000: begin grant_onehot_r = 8'b00010000; grant_index_r = LOG_NUM_REQS'(4); end
11'b111_???10000: begin grant_index_r = LOG_NUM_REQS'(4); end
11'b000_??10000?,
11'b001_??1000??,
11'b010_??100???,
@ -349,7 +369,7 @@ module VX_rr_arbiter #(
11'b100_??1?????,
11'b101_00100000,
11'b110_0?100000,
11'b111_??100000: begin grant_onehot_r = 8'b00100000; grant_index_r = LOG_NUM_REQS'(5); end
11'b111_??100000: begin grant_index_r = LOG_NUM_REQS'(5); end
11'b000_?100000?,
11'b001_?10000??,
11'b010_?1000???,
@ -357,8 +377,16 @@ module VX_rr_arbiter #(
11'b100_?10?????,
11'b101_?1??????,
11'b110_01000000,
11'b111_?1000000: begin grant_onehot_r = 8'b01000000; grant_index_r = LOG_NUM_REQS'(6); end
default: begin grant_onehot_r = 8'b10000000; grant_index_r = LOG_NUM_REQS'(7); end
11'b111_?1000000: begin grant_index_r = LOG_NUM_REQS'(6); end
11'b000_1000000?,
11'b001_100000??,
11'b010_10000???,
11'b011_1000????,
11'b100_100?????,
11'b101_10??????,
11'b110_1???????,
11'b111_10000000: begin grant_index_r = LOG_NUM_REQS'(7); end
default: begin grant_index_r = 'x; end
endcase
end
@ -371,7 +399,7 @@ module VX_rr_arbiter #(
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_valid = (| requests);
end else if (MODEL == 1) begin
@ -393,8 +421,8 @@ module VX_rr_arbiter #(
assign unmasked_pri_reqs[i] = unmasked_pri_reqs[i-1] | requests[i-1];
end
wire [NUM_REQS-1:0] grant_masked = masked_reqs & ~masked_pri_reqs[NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_unmasked = requests & ~unmasked_pri_reqs[NUM_REQS-1:0];
wire [NUM_REQS-1:0] grant_masked = masked_reqs & ~masked_pri_reqs;
wire [NUM_REQS-1:0] grant_unmasked = requests & ~unmasked_pri_reqs;
wire has_masked_reqs = (| masked_reqs);
wire has_unmasked_reqs = (| requests);
@ -421,41 +449,34 @@ module VX_rr_arbiter #(
.valid_out(grant_valid)
);
end else begin
end else if (MODEL == 2) begin
reg grant_valid_r;
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
reg [NUM_REQS-1:0][LOG_NUM_REQS-1:0] next_grant_index;
reg [LOG_NUM_REQS-1:0] grant_table [NUM_REQS-1:0];
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
grant_valid_r = 0;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (requests[next_grant_index[i]]) begin
grant_valid_r = 1;
grant_index_r = next_grant_index[i];
grant_onehot_r = NUM_REQS'(1) << next_grant_index[i];
for (genvar i = 0; i < NUM_REQS; ++i) begin
always @(*) begin
grant_table[i] = 'x;
for (integer j = NUM_REQS-1; j >= 0; --j) begin
if (requests[(i+j+1) % NUM_REQS]) begin
grant_table[i] = LOG_NUM_REQS'(i+j+1);
end
end
end
end
always @(posedge clk) begin
if (reset) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
next_grant_index[i] <= LOG_NUM_REQS'(i);
end
state <= 0;
end else if (grant_valid && grant_ready) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
next_grant_index[i] <= grant_index_r + LOG_NUM_REQS'(i + 1);
end
state <= grant_index;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = grant_valid_r;
assign grant_index = grant_table[state];
assign grant_onehot = NUM_REQS'(1) << grant_index;
assign grant_valid = (| requests);
end
endmodule

2
hw/rtl/mem/VX_local_mem.sv
View file

@ -121,7 +121,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.NUM_OUTPUTS (NUM_BANKS),
.DATAW (REQ_DATAW),
.PERF_CTR_BITS (`PERF_CTR_BITS),
.ARBITER ("F"),
.ARBITER ("R"),
.OUT_BUF (3) // output should be registered for the data_store addressing
) req_xbar (
.clk (clk),