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minor updates

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This commit is contained in:
Blaise Tine 2023-04-16 18:43:32 -04:00
parent 912521a205
commit ed9e9d9257
2 changed files with 72 additions and 37 deletions
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98
hw/rtl/libs/VX_pending_size.sv
View file

@ -3,57 +3,87 @@
`TRACING_OFF
module VX_pending_size #(
parameter SIZE = 1,
parameter INCRW = 1,
parameter DECRW = 1,
parameter SIZEW = $clog2(SIZE+1)
) (
input wire clk,
input wire reset,
input wire incr,
input wire decr,
input wire [INCRW-1:0] incr,
input wire [DECRW-1:0] decr,
output wire empty,
output wire full,
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(INCRW <= SIZEW, ("invalid parameter"))
`STATIC_ASSERT(DECRW <= SIZEW, ("invalid parameter"))
localparam ADDRW = `LOG2UP(SIZE);
reg [ADDRW-1:0] used_r;
reg empty_r;
reg full_r;
reg empty_r;
reg full_r;
always @(posedge clk) begin
if (reset) begin
used_r <= '0;
empty_r <= 1;
full_r <= 0;
end else begin
`ASSERT(~(incr && ~decr) || ~full, ("runtime error: incrementing full counter"));
`ASSERT(~(decr && ~incr) || ~empty, ("runtime error: decrementing empty counter"));
if (incr) begin
if (~decr) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
end else if (decr) begin
full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
if (INCRW != 1 || DECRW != 1) begin
reg [SIZEW-1:0] size_r;
wire [SIZEW-1:0] size_n;
assign size_n = size_r + SIZEW'(incr) - SIZEW'(decr);
always @(posedge clk) begin
if (reset) begin
size_r <= '0;
empty_r <= 1;
full_r <= 0;
end else begin
size_r <= size_n;
empty_r <= (size_n == SIZEW'(0));
full_r <= (size_n == SIZEW'(SIZE));
end
used_r <= $signed(used_r) + ADDRW'($signed(2'(incr) - 2'(decr)));
end
assign size = size_r;
end else begin
reg [ADDRW-1:0] used_r;
always @(posedge clk) begin
if (reset) begin
used_r <= '0;
empty_r <= 1;
full_r <= 0;
end else begin
`ASSERT(~(incr && ~decr) || ~full, ("runtime error: incrementing full counter"));
`ASSERT(~(decr && ~incr) || ~empty, ("runtime error: decrementing empty counter"));
if (incr) begin
if (~decr) begin
empty_r <= 0;
if (used_r == ADDRW'(SIZE-1))
full_r <= 1;
end
end else if (decr) begin
full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
end
used_r <= $signed(used_r) + ADDRW'($signed(2'(incr) - 2'(decr)));
end
end
if (SIZE > 1) begin
if (SIZEW > ADDRW) begin
assign size = {full_r, used_r};
end else begin
assign size = used_r;
end
end else begin
assign size = full_r;
end
end
assign empty = empty_r;
assign full = full_r;
if (SIZE > 1) begin
if (SIZEW > ADDRW) begin
assign size = {full_r, used_r};
end else begin
assign size = used_r;
end
end else begin
assign size = full_r;
end
endmodule
`TRACING_ON

11
hw/rtl/raster_unit/VX_raster_unit.sv
View file

@ -30,6 +30,7 @@ module VX_raster_unit #(
VX_raster_req_if.master raster_req_if
);
localparam EDGE_FUNC_LATENCY = `LATENCY_IMUL;
localparam SLICES_BITS = $clog2(NUM_SLICES+1);
// A primitive data contains (xloc, yloc, pid, edges, extents)
localparam PRIM_DATA_WIDTH = 2 * `RASTER_DIM_BITS + `RASTER_PID_BITS + 9 * `RASTER_DATA_BITS + 3 * `RASTER_DATA_BITS;
@ -174,15 +175,19 @@ module VX_raster_unit #(
wire no_pending_tiledata;
wire mem_unit_fire = mem_unit_valid && mem_unit_ready;
wire slice_arb_fire_out = | (slice_arb_valid_out & slice_arb_ready_out);
wire [NUM_SLICES-1:0] slice_arb_fire_out = slice_arb_valid_out & slice_arb_ready_out;
wire [SLICES_BITS-1:0] slice_arb_fire_out_cnt;
`POP_COUNT(slice_arb_fire_out_cnt, slice_arb_fire_out);
VX_pending_size #(
.SIZE (EDGE_FUNC_LATENCY + 2 * NUM_SLICES)
.SIZE (EDGE_FUNC_LATENCY + 2 * NUM_SLICES),
.DECRW (SLICES_BITS)
) pending_slice_inputs (
.clk (clk),
.reset (reset),
.incr (mem_unit_fire),
.decr (slice_arb_fire_out),
.decr (slice_arb_fire_out_cnt),
.empty (no_pending_tiledata),
`UNUSED_PIN (size),
`UNUSED_PIN (full)