VX_onehot_encoder update

hw/rtl/VX_platform.vh

@@ -37,9 +37,11 @@ endgenerate
 `define ASSERT(cond, msg) \
     assert(cond) else $error msg
 
-`define RUNTIME_ASSERT(cond, msg)     \
-    always @(posedge clk) begin       \
-        assert(cond) else $error msg; \
+`define RUNTIME_ASSERT(cond, msg) \
+    always @(posedge clk) begin   \
+        if (!reset) begin         \
+            `ASSERT(cond, msg);   \
+        end                       \
     end
 
 `define __SCOPE
@@ -172,6 +174,7 @@ endgenerate
 `ifdef QUARTUS
 `define MAX_FANOUT      8
 `define IF_DATA_SIZE(x) $bits(x.data)
+`define USE_BLOCK_BRAM  (* ramstyle = "block" *)
 `define USE_FAST_BRAM   (* ramstyle = "MLAB, no_rw_check" *)
 `define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
 `define DISABLE_BRAM    (* ramstyle = "logic" *)
@@ -180,6 +183,7 @@ endgenerate
 `elsif VIVADO
 `define MAX_FANOUT      8
 `define IF_DATA_SIZE(x) $bits(x.data)
+`define USE_BLOCK_BRAM  (* ram_style = "block" *)
 `define USE_FAST_BRAM   (* ram_style = "distributed" *)
 `define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *)
 `define DISABLE_BRAM    (* ram_style = "registers" *)
@@ -188,6 +192,7 @@ endgenerate
 `else
 `define MAX_FANOUT      8
 `define IF_DATA_SIZE(x) x.DATA_WIDTH
+`define USE_BLOCK_BRAM
 `define USE_FAST_BRAM
 `define NO_RW_RAM_CHECK
 `define DISABLE_BRAM

hw/rtl/afu/opae/vortex_afu.sv

@@ -968,7 +968,7 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
 
     wire [COUT_TID_WIDTH-1:0] cout_tid;
 
-    VX_encoder #(
+    VX_onehot_encoder #(
         .N (`VX_MEM_BYTEEN_WIDTH)
     ) cout_tid_enc (
         .data_in  (vx_mem_req_byteen),

hw/rtl/cache/VX_cache_data.sv

@@ -73,7 +73,7 @@ module VX_cache_data #(
 
     assign line_idx = line_addr[`CS_LINE_SEL_BITS-1:0];
 
-    VX_encoder #(
+    VX_onehot_encoder #(
         .N (NUM_WAYS)
     ) way_idx_enc (
         .data_in  (way_idx),

hw/rtl/cache/VX_cache_mshr.sv

@@ -148,11 +148,12 @@ module VX_cache_mshr #(
         .valid_out (allocate_rdy_n)
     );
 
-    VX_encoder #(
+    VX_priority_encoder #(
         .N (MSHR_SIZE)
     ) prev_sel (
         .data_in (addr_matches & ~next_table_x),
-        .data_out (prev_idx),
+        .index_out (prev_idx),
+        `UNUSED_PIN (onehot_out),
         `UNUSED_PIN (valid_out)
     );
 

hw/rtl/libs/VX_matrix_arbiter.sv

@@ -72,7 +72,7 @@ module VX_matrix_arbiter #(
 
         assign grant_onehot = grant;
 
-        VX_encoder #(
+        VX_onehot_encoder #(
             .N (NUM_REQS)
         ) encoder (
             .data_in   (grant_onehot),

hw/rtl/libs/VX_onehot_encoder.sv

@@ -13,11 +13,11 @@
 
 `include "VX_platform.vh"
 
-// Fast encoder using parallel prefix computation
+// Fast one-hot encoder using parallel prefix computation
 // Adapted from BaseJump STL: http://bjump.org/data_out.html
 
 `TRACING_OFF
-module VX_encoder #(
+module VX_onehot_encoder #(
     parameter N       = 1,
     parameter REVERSE = 0,
     parameter MODEL   = 1,

hw/rtl/libs/VX_pending_size.sv

@@ -66,11 +66,13 @@ module VX_pending_size #(
 
         if (INCRW != 1 || DECRW != 1) begin : g_wide_step
 
-            localparam SUBW = `MIN(SIZEW, `MAX(INCRW, DECRW)+1);
+            localparam DELTAW = `MIN(SIZEW, `MAX(INCRW, DECRW)+1);
 
             logic [SIZEW-1:0] size_n, size_r;
 
-            assign size_n = $signed(size_r) + SIZEW'($signed(SUBW'(incr) - SUBW'(decr)));
+            wire [DELTAW-1:0] delta = DELTAW'(incr) - DELTAW'(decr);
+
+            assign size_n = $signed(size_r) + SIZEW'($signed(delta));
 
             always @(posedge clk) begin
                 if (reset) begin
@@ -80,8 +82,8 @@ module VX_pending_size #(
                     alm_full_r  <= 0;
                     size_r      <= '0;
                 end else begin
-                    `ASSERT((SIZEW'(incr) >= SIZEW'(decr)) || (size_n >= size_r), ("runtime error: counter overflow"));
-                    `ASSERT((SIZEW'(incr) <= SIZEW'(decr)) || (size_n <= size_r), ("runtime error: counter underflow"));
+                    `ASSERT((DELTAW'(incr) <= DELTAW'(decr)) || (size_n >= size_r), ("runtime error: counter overflow"));
+                    `ASSERT((DELTAW'(incr) >= DELTAW'(decr)) || (size_n <= size_r), ("runtime error: counter underflow"));
                     empty_r     <= (size_n == SIZEW'(0));
                     full_r      <= (size_n == SIZEW'(SIZE));
                     alm_empty_r <= (size_n <= SIZEW'(ALM_EMPTY));
@@ -129,7 +131,7 @@ module VX_pending_size #(
                 wire is_empty_n = (used_r == ADDRW'(1));
                 wire is_full_n  = (used_r == ADDRW'(SIZE-1));
 
-                wire [1:0] push_minus_pop = {~incr & decr, incr ^ decr};
+                wire [1:0] delta = {~incr & decr, incr ^ decr};
 
                 always @(posedge clk) begin
                     if (reset) begin
@@ -148,7 +150,7 @@ module VX_pending_size #(
                             if (is_empty_n)
                                 empty_r <= 1;
                         end
-                        used_r <= $signed(used_r) + ADDRW'($signed(push_minus_pop));
+                        used_r <= $signed(used_r) + ADDRW'($signed(delta));
                     end
                 end
 

hw/rtl/libs/VX_rr_arbiter.sv

@@ -448,7 +448,7 @@ module VX_rr_arbiter #(
 			end
 	    end
 
-        VX_encoder #(
+        VX_onehot_encoder #(
             .N (NUM_REQS)
         ) onehot_encoder (
             .data_in  (grant_onehot),