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Update rv32ui test files

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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
This commit is contained in:
Ruei-Ting Chien 2020-02-23 02:23:27 -05:00
commit ef2c8f3cb9
49 changed files with 27510 additions and 3 deletions
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docs/Vortex.pptx
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rtl/cache/Makefile vendored
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@ -2,7 +2,7 @@ all: RUNFILE
VERILATOR:
verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Iinterfaces/ --exe d_cache_test_bench.cpp -CFLAGS -std=c++11
verilator --compiler gcc --Wno-UNOPTFLAT -Wall --trace -cc VX_d_cache_encapsulate.v -Irtl --exe d_cache_test_bench.cpp -CFLAGS -std=c++11
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVX_d_cache_encapsulate.mk)

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rtl/cache/VX_d_cache_encapsulate.v vendored
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@ -1,5 +1,5 @@
`include "VX_define.v"
`include "../VX_define.v"
// `define NUM_WORDS_PER_BLOCK 4

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simX/obj_dir/Vcache_simX.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vcache_simX_H_
#define _Vcache_simX_H_
#include "verilated.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_Cache_Bank__pi8;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
VL_SIG8(cache_simX__DOT__icache_i_m_ready,0,0);
VL_SIG8(cache_simX__DOT__dcache_i_m_ready,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__read_or_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid,3,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we,7,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num,7,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank,7,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank,3,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__valid_use,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__access,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__write_from_mem,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__way_to_update,0,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__we,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__valid_use_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__dirty_use_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__hit_per_way,1,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__we_per_way,31,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__write_from_mem_per_way,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__invalid_index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__way_use_Qual,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata,511,0,16);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank,127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__tag_use,22,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_unQual,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_write,127,0,4);
VL_SIG64(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__tag_use_per_way,45,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_use_per_way,255,0,8);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__data_write_per_way,255,0,8);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4],3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[1],0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],22,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],22,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__DOT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16],1,0);
static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16],0,0);
static VL_ST_SIG(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1,6,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2,6,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__multip_banks__DOT____Vlvbound1,0,0);
VL_SIG8(__Vtableidx1,3,0);
VL_SIG8(__Vtableidx2,3,0);
VL_SIG8(__Vtableidx3,3,0);
VL_SIG8(__Vtableidx4,3,0);
VL_SIG8(__Vtableidx5,3,0);
VL_SIG8(__Vtableidx6,3,0);
VL_SIG8(__Vtableidx7,3,0);
VL_SIG8(__Vtableidx8,3,0);
VL_SIG8(__Vtableidx9,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address,127,0,4);
VL_SIG(__Vm_traceActivity,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vcache_simX__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
Vcache_simX& operator= (const Vcache_simX&); ///< Copying not allowed
Vcache_simX(const Vcache_simX&); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible WRT DPI scope names.
Vcache_simX(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vcache_simX();
/// Trace signals in the model; called by application code
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
static void _eval(Vcache_simX__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp);
static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

85
simX/obj_dir/Vcache_simX.mk Normal file
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@ -0,0 +1,85 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vcache_simX.mk
default: Vcache_simX
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vcache_simX
# Module prefix (from --prefix)
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
args \
core \
enc \
instruction \
mem \
simX \
util \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include Vcache_simX_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
args.o: args.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
core.o: core.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
enc.o: enc.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
instruction.o: instruction.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
mem.o: mem.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
simX.o: simX.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
util.o: util.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt
# Verilated -*- Makefile -*-

7165
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp Normal file
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230
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h Normal file
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@ -0,0 +1,230 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_Cache_Bank__pi8_H_
#define _Vcache_simX_VX_Cache_Bank__pi8_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
public:
// PORTS
VL_IN8(rst,0,0);
VL_IN8(clk,0,0);
VL_IN8(state,3,0);
VL_IN8(actual_index,4,0);
VL_IN8(block_offset,1,0);
VL_IN8(valid_in,0,0);
VL_IN8(read_or_write,0,0);
VL_IN8(i_p_mem_read,2,0);
VL_IN8(i_p_mem_write,2,0);
VL_IN8(byte_select,1,0);
VL_IN8(evicted_way,0,0);
VL_OUT8(hit,0,0);
VL_OUT8(eviction_wb,0,0);
VL_IN(o_tag,20,0);
VL_IN(writedata,31,0);
VL_INW(fetched_writedata,127,0,4);
VL_OUT(readdata,31,0);
VL_OUT(eviction_addr,31,0);
VL_OUTW(data_evicted,127,0,4);
// LOCAL SIGNALS
VL_SIG8(__PVT__valid_use,0,0);
VL_SIG8(__PVT__access,0,0);
VL_SIG8(__PVT__write_from_mem,0,0);
VL_SIG8(__PVT__way_to_update,0,0);
VL_SIG8(__PVT__sb_mask,3,0);
VL_SIG16(__PVT__we,15,0);
VL_SIG8(__PVT__genblk1__BRA__0__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__data_structures__DOT__valid_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__dirty_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__hit_per_way,1,0);
VL_SIG(__PVT__data_structures__DOT__we_per_way,31,0);
VL_SIG8(__PVT__data_structures__DOT__write_from_mem_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__invalid_found,0,0);
VL_SIG8(__PVT__data_structures__DOT__way_index,0,0);
VL_SIG8(__PVT__data_structures__DOT__invalid_index,0,0);
VL_SIG8(__PVT__data_structures__DOT__way_use_Qual,0,0);
VL_SIG8(__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__update_dirty,0,0);
VL_SIG(__PVT__tag_use,20,0);
VL_SIG(__PVT__data_unQual,31,0);
VL_SIG(__PVT__use_write_data,31,0);
VL_SIGW(__PVT__data_write,127,0,4);
VL_SIG64(__PVT__data_structures__DOT__tag_use_per_way,41,0);
VL_SIGW(__PVT__data_structures__DOT__data_use_per_way,255,0,8);
VL_SIGW(__PVT__data_structures__DOT__data_write_per_way,255,0,8);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],20,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0);
VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],20,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
// LOCAL VARIABLES
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0,0,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v40,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v41,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,0,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,0,0);
VL_SIGW(__Vcellout__data_structures__data_use,127,0,4);
VL_SIG(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,20,0);
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// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_Cache_Bank__pi8& operator= (const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed
Vcache_simX_VX_Cache_Bank__pi8(const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed
public:
Vcache_simX_VX_Cache_Bank__pi8(const char* name="TOP");
~Vcache_simX_VX_Cache_Bank__pi8();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

37
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp Normal file
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@ -0,0 +1,37 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dcache_request_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dcache_request_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,out_cache_driver_in_address);
out_cache_driver_in_valid = VL_RAND_RESET_I(4);
}

54
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h Normal file
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@ -0,0 +1,54 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_request_inter_H_
#define _Vcache_simX_VX_dcache_request_inter_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_request_inter) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIG8(out_cache_driver_in_valid,3,0);
VL_SIGW(out_cache_driver_in_address,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_request_inter& operator= (const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_request_inter(const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_request_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

36
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,i_m_readdata);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIGW(i_m_readdata,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(512,i_m_readdata);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIGW(i_m_readdata,511,0,16);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

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simX/obj_dir/Vcache_simX__ALLcls.cpp Normal file
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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi8.cpp"

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Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
Vcache_simX.h /usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_Cache_Bank__pi8.cpp

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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX__Trace.cpp"
#include "Vcache_simX__Syms.cpp"
#include "Vcache_simX__Trace__Slow.cpp"

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Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h Vcache_simX__Syms.h \
/usr/share/verilator/include/verilated.h Vcache_simX.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX__Syms.cpp Vcache_simX__Trace__Slow.cpp

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// FUNCTIONS
Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
, TOP__cache_simX__DOT__VX_dcache_req (Verilated::catName(topp->name(),"cache_simX.VX_dcache_req"))
, TOP__cache_simX__DOT__VX_dram_req_rsp (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp"))
, TOP__cache_simX__DOT__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _Vcache_simX__Syms_H_
#define _Vcache_simX__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// SYMS CLASS
class Vcache_simX__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
// SUBCELL STATE
Vcache_simX* TOPp;
Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
~Vcache_simX__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
} VL_ATTR_ALIGNED(64);
#endif // guard

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simX/obj_dir/Vcache_simX__ver.d Normal file
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obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v

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# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 4200738 1579395713 628434579 1579395713 628434579 "../rtl/./VX_define_synth.v"
S 283 4200733 1579395713 624434332 1579395713 624434332 "../rtl/VX_countones.v"
S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/VX_define.v"
S 8325 4200739 1579395713 628434579 1579395713 628434579 "../rtl/VX_dmem_controller.v"
S 517 4200743 1579395713 628434579 1579395713 628434579 "../rtl/VX_generic_priority_encoder.v"
S 683 4200754 1579395713 628434579 1579395713 628434579 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 4200764 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_Cache_Bank.v"
S 748 4200765 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 4200766 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data.v"
S 6476 4200767 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 4200768 1579395713 628434579 1579395713 628434579 "../rtl/cache/VX_d_cache.v"
S 393 4200780 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 4200781 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 4200782 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 4200791 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 4200792 1579395713 628434579 1579395713 628434579 "../rtl/interfaces/VX_icache_response_inter.v"
S 7240 4200737 1579395713 628434579 1579395713 628434579 "../rtl/shared_memory/../VX_define.v"
S 676 4200836 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 4200837 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 4200838 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 4200839 1579395713 632434826 1579395713 632434826 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 2492902 1578745602 593855204 1519110675 0 "/usr/bin/verilator_bin"
S 3144 4201058 1579395714 588493892 1579395714 588493892 "cache_simX.v"
T 606556 4194579 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX.cpp"
T 31121 4194577 1579629057 321619018 1579629057 321619018 "obj_dir/Vcache_simX.h"
T 2305 4196430 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX.mk"
T 539818 4194597 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 19062 4194595 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 1024 4194591 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 4194589 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 4194587 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
T 1556 4194585 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
T 999 4194583 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 4194581 1579629057 329619018 1579629057 329619018 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 3807 4194517 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.cpp"
T 1918 4194514 1579629057 293619017 1579629057 293619017 "obj_dir/Vcache_simX__Syms.h"
T 704422 4194575 1579629057 317619018 1579629057 317619018 "obj_dir/Vcache_simX__Trace.cpp"
T 921157 4194573 1579629057 309619018 1579629057 309619018 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1461 4196431 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__ver.d"
T 0 0 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX__verFiles.dat"
T 1403 4196429 1579629057 341619018 1579629057 341619018 "obj_dir/Vcache_simX_classes.mk"

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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vcache_simX.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_Cache_Bank__pi8 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
Vcache_simX__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vcache_simX__Syms \
Vcache_simX__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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args.o: ../args.cpp ../include/args.h

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core.o: ../core.cpp ../include/types.h ../include/util.h \
../include/types.h ../include/archdef.h ../include/mem.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/archdef.h ../include/enc.h \
../include/asm-tokens.h ../include/core.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/debug.h

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../rvvector/basic/vx_vector_main.hex not found

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enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/archdef.h \
../include/enc.h ../include/asm-tokens.h ../include/archdef.h \
../include/instruction.h

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instruction.o: ../instruction.cpp ../include/instruction.h \
../include/types.h ../include/trace.h ../include/obj.h \
../include/archdef.h ../include/instruction.h ../include/enc.h \
../include/obj.h ../include/asm-tokens.h ../include/core.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/harpfloat.h \
../include/debug.h

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mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/mem.h ../include/core.h \
../include/archdef.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/asm-tokens.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h

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simX.o: ../simX.cpp ../include/debug.h ../include/types.h \
../include/core.h ../include/types.h ../include/archdef.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/asm-tokens.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/enc.h \
../include/instruction.h ../include/mem.h ../include/obj.h \
../include/archdef.h ../include/args.h ../include/help.h

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util.o: ../util.cpp ../include/types.h ../include/util.h \
../include/types.h

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verilated.o: /usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_imp.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_heavy.h \
/usr/share/verilator/include/verilated_syms.h

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verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_vcd_c.h

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# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug