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https://github.com/vortexgpgpu/vortex.git
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cache regression tests
This commit is contained in:
Blaise Tine
parent
4dc34cfd2d
commit
ef5d58dc9e
2 changed files with 87 additions and 69 deletions
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@ -122,32 +122,54 @@ opencl()
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echo "opencl tests done!"
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}
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test_csv_trace()
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cache()
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{
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# test CSV trace generation
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make -C sim/simx clean && DEBUG=3 make -C sim/simx > /dev/null
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make -C sim/rtlsim clean && DEBUG=3 CONFIGS="-DGPR_RESET" make -C sim/rtlsim > /dev/null
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make -C tests/riscv/isa run-simx-32im > run_simx.log
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make -C tests/riscv/isa run-rtlsim-32im > run_rtlsim.log
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./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv
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./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv
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diff trace_rtlsim.csv trace_simx.csv
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# clean build
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make -C sim/simx clean
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make -C sim/rtlsim clean
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}
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echo "begin cache tests..."
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debug()
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{
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echo "begin debugging tests..."
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# disable local memory
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CONFIGS="-DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=demo --perf=1
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CONFIGS="-DLMEM_DISABLE" ./ci/blackbox.sh --driver=simx --app=demo --perf=1
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test_csv_trace
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# disable L1 cache
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CONFIGS="-DL1_DISABLE -DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DL1_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DICACHE_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
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./ci/blackbox.sh --driver=opae --cores=1 --scope --app=demo --args="-n1"
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# reduce l1 line size
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8" ./ci/blackbox.sh --driver=rtlsim --app=io_addr
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8" ./ci/blackbox.sh --driver=simx --app=io_addr
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8 -DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8 -DLMEM_DISABLE" ./ci/blackbox.sh --driver=simx --app=sgemmx
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echo "debugging tests done!"
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# test cache ways
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CONFIGS="-DICACHE_NUM_WAYS=8 -DDCACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DICACHE_NUM_WAYS=8 -DDCACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=simx --app=sgemmx
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# test cache banking
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CONFIGS="-DLMEM_NUM_BANKS=4 -DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DLMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DLMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemmx
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# test writeback
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CONFIGS="-DDCACHE_WRITEBACK=1" ./ci/blackbox.sh --driver=rtlsim --app=mstress
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CONFIGS="-DDCACHE_WRITEBACK=1" ./ci/blackbox.sh --driver=simx --app=mstress
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CONFIGS="-DSOCKET_SIZE=1 -DDCACHE_WRITEBACK=1 -DL2_WRITEBACK=1 -DL3_WRITEBACK=1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=mstress
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CONFIGS="-DSOCKET_SIZE=1 -DDCACHE_WRITEBACK=1 -DL2_WRITEBACK=1 -DL3_WRITEBACK=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --l3cache --app=mstress
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# cache clustering
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CONFIGS="-DSOCKET_SIZE=4 -DNUM_DCACHES=4 -DNUM_ICACHES=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx --cores=4 --warps=1 --threads=2
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# L2/L3
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=4 --l2cache --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --l3cache --app=diverge --args="-n1"
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echo "begin cache tests..."
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}
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config1()
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@ -163,10 +185,12 @@ config1()
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./ci/blackbox.sh --driver=simx --warps=8 --threads=16 --app=diverge
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# cores clustering
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./ci/blackbox.sh --driver=rtlsim --cores=4 --clusters=1 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=4 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=4 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=1 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --app=diverge --args="-n1"
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# issue width
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CONFIGS="-DISSUE_WIDTH=2" ./ci/blackbox.sh --driver=rtlsim --app=diverge
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@ -192,16 +216,6 @@ config1()
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CONFIGS="-DISSUE_WIDTH=2 -DNUM_LSU_BLOCK=1 -DNUM_LSU_LANES=2" ./ci/blackbox.sh --driver=simx --app=vecaddx
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CONFIGS="-DISSUE_WIDTH=4 -DNUM_LSU_BLOCK=4 -DNUM_LSU_LANES=4" ./ci/blackbox.sh --driver=simx --app=vecaddx
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# L2/L3
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=diverge --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l3cache --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=io_addr --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=2 --l2cache --app=diverge --args="-n1"
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./ci/blackbox.sh --driver=simx --cores=4 --clusters=4 --l2cache --l3cache --app=diverge --args="-n1"
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# multiple L1 caches per socket
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CONFIGS="-DSOCKET_SIZE=4 -DNUM_DCACHES=2 -DNUM_ICACHES=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx --cores=8 --warps=1 --threads=2
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echo "configuration-1 tests done!"
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}
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@ -232,37 +246,9 @@ config2()
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# disabling ZICOND extension
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CONFIGS="-DEXT_ZICOND_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=demo
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# disable local memory
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CONFIGS="-DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=demo --perf=1
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CONFIGS="-DLMEM_DISABLE" ./ci/blackbox.sh --driver=simx --app=demo --perf=1
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# test AXI bus
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AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --app=demo
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# disable L1 cache
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CONFIGS="-DL1_DISABLE -DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DL1_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DICACHE_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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# reduce l1 line size
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8" ./ci/blackbox.sh --driver=rtlsim --app=io_addr
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8" ./ci/blackbox.sh --driver=simx --app=io_addr
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8 -DLMEM_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DL1_LINE_SIZE=$XLEN/8 -DLMEM_DISABLE" ./ci/blackbox.sh --driver=simx --app=sgemmx
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# test cache ways
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CONFIGS="-DICACHE_NUM_WAYS=8 -DDCACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DICACHE_NUM_WAYS=8 -DDCACHE_NUM_WAYS=8" ./ci/blackbox.sh --driver=simx --app=sgemmx
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# test cache banking
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CONFIGS="-DLMEM_NUM_BANKS=4 -DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DLMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DLMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx
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CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemmx
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# test 128-bit MEM block
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CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=opae --app=demo
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@ -275,12 +261,40 @@ config2()
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echo "configuration-2 tests done!"
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}
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test_csv_trace()
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{
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# test CSV trace generation
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make -C sim/simx clean && DEBUG=3 make -C sim/simx > /dev/null
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make -C sim/rtlsim clean && DEBUG=3 CONFIGS="-DGPR_RESET" make -C sim/rtlsim > /dev/null
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make -C tests/riscv/isa run-simx-32im > run_simx.log
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make -C tests/riscv/isa run-rtlsim-32im > run_rtlsim.log
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./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv
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./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv
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diff trace_rtlsim.csv trace_simx.csv
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# clean build
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make -C sim/simx clean
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make -C sim/rtlsim clean
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}
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debug()
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{
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echo "begin debugging tests..."
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test_csv_trace
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
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CONFIGS="-DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --debug=1 --perf=1 --app=demo --args="-n1"
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./ci/blackbox.sh --driver=opae --cores=1 --scope --app=demo --args="-n1"
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echo "debugging tests done!"
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}
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stress()
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{
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echo "begin stress tests..."
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# test verilator reset values
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CONFIGS="-DVERILATOR_RESET_VALUE=1 -DSOCKET_SIZE=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood
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CONFIGS="-DVERILATOR_RESET_VALUE=1 -DSOCKET_SIZE=1 -DDCACHE_WRITEBACK=1 -DL2_WRITEBACK=1 -DL3_WRITEBACK=1" ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --l3cache --app=dogfood
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CONFIGS="-DVERILATOR_RESET_VALUE=1" ./ci/blackbox.sh --driver=rtlsim --app=sgemmx --args="-n128" --l2cache
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echo "stress tests done!"
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@ -299,11 +313,9 @@ synthesis()
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show_usage()
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{
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echo "Vortex Regression Test"
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echo "Usage: $0 [--clean] [--unittest] [--isa] [--kernel] [--regression] [--opencl] [--config1] [--config2] [--debug] [--stress] [--synthesis] [--all] [--h|--help]"
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echo "Usage: $0 [--clean] [--unittest] [--isa] [--kernel] [--regression] [--opencl] [--cache] [--config1] [--config2] [--debug] [--stress] [--synthesis] [--all] [--h|--help]"
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}
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start=$SECONDS
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declare -a tests=()
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clean=0
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@ -327,6 +339,9 @@ while [ "$1" != "" ]; do
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--opencl )
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tests+=("opencl")
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;;
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--cache )
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tests+=("cache")
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;;
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--config1 )
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tests+=("config1")
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;;
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@ -349,6 +364,7 @@ while [ "$1" != "" ]; do
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tests+=("kernel")
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tests+=("regression")
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tests+=("opencl")
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tests+=("cache")
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tests+=("config1")
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tests+=("config2")
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tests+=("debug")
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@ -372,6 +388,8 @@ then
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make -s
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fi
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start=$SECONDS
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for test in "${tests[@]}"; do
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$test
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done
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@ -537,7 +537,7 @@
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// Enable Cache Writeback
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`ifndef DCACHE_WRITEBACK
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`define DCACHE_WRITEBACK 1
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`define DCACHE_WRITEBACK 0
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`endif
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// LMEM Configurable Knobs ////////////////////////////////////////////////////
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@ -601,7 +601,7 @@
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// Enable Cache Writeback
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`ifndef L2_WRITEBACK
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`define L2_WRITEBACK 1
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`define L2_WRITEBACK 0
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`endif
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// L3cache Configurable Knobs /////////////////////////////////////////////////
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@ -647,7 +647,7 @@
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// Enable Cache Writeback
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`ifndef L3_WRITEBACK
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`define L3_WRITEBACK 1
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`define L3_WRITEBACK 0
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`endif
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// ISA Extensions /////////////////////////////////////////////////////////////
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